A166 MACRO ASSEMBLER START 01/12/05 22:15:52 PAGE 1 DOS MACRO ASSEMBLER A166 V3.10 OBJECT MODULE PLACED IN ..\RAM\INC\START.OBJ ASSEMBLER INVOKED BY: C:\C166\BIN\A166.EXE ..\RAM\INC\START.A66 CASE MOD167 SEGMENTED SET(LARGE) LOC OBJ LINE SOURCE 1 $MOD167 ; Define C167 mode 2 ; 3 ;------------------------------------------------------------------------------ 4 ; This file is part of the C166 Compiler package 5 ; Copyright KEIL ELEKTRONIK GmbH 1993-1999 6 ; Version 4.01 7 ; Modified by Phytec 12.08.1999 8 ;------------------------------------------------------------------------------ 9 ; START167.A66: This code is executed after processor reset and provides the 10 ; startup sequence for the extended 166 architecture CPU's. 11 ; (i.e. C167/C165/C164/C163/C161, ST10-262 ect.) 12 ; 13 ; To translate this file use A166 with the following invocation: 14 ; 15 ; A166 START167.A66 SET () 16 ; 17 ; determines the memory model and can be one of the following: 18 ; TINY, SMALL, COMPACT, HCOMPACT, MEDIUM, LARGE or HLARGE 19 ; 20 ; Example: A166 START167.A66 SET (SMALL) 21 ; 22 ; To link the modified START167.OBJ file to your application use the following 23 ; L166 invocation: 24 ; 25 ; L166 , START167.OBJ 26 ; 27 ;------------------------------------------------------------------------------ 28 ; Setup model-dependend Assembler controls 29 $CASE 30 $IF NOT TINY 31 $SEGMENTED 32 $ENDIF 33 ;------------------------------------------------------------------------------ 34 ; 35 ; Definitions for BUSCON0 and SYSCON Register: 36 ; -------------------------------------------- 37 ; 38 ; MCTC0: Memory Cycle Time (BUSCON0.0 .. BUSCON0.3): 39 ; Note: if RDYEN0 == 1 a maximum number of 7 waitstates can be selected 40 _MCTC0 EQU 2 ; Memory wait states is 1 (MCTC0 field = 0EH). 41 ; ; (Reset Value = 15 additional state times) 42 ; 43 ; RWDC0: Read/Write Signal Delay (BUSCON0.4): 44 _RWDC0 EQU 1 ; 0 = Delay Time 0.5 States (Reset Value) 45 ; ; 1 = No Delay Time 0 States 46 ; 47 ; MTTC0: Memory Tri-state Time (BUSCON0.5): 48 _MTTC0 EQU 1 ; 0 = Delay Time 0.5 States (Reset Value, 0 this is the default) 49 ; ; 1 = No Delay Time 0 States 50 ; 51 $SET (BTYP_ENABLE = 0) ; 0 = BTYP0 and BUSACT0 is set according to the level 52 ; at pins P0L.6, P0L.7, and EA# during reset. 53 ; 1 = the following _BTYP0 and _BUSACT0 values are 54 ; written to BTYP0 and BUSACT0 55 ; 56 ; BTYP0: External Bus Configuration Control (BUSCON0.6 .. BUSCON0.7): 57 _BTYP0 EQU 2 ; 0 = 8 Bit Non Multiplexed 58 ; ; 1 = 8 Bit Multiplexed 59 ; ; 2 = 16 Bit Non Multiplexed A166 MACRO ASSEMBLER START 01/12/05 22:15:52 PAGE 2 60 ; ; 3 = 16 Bit Multiplexed 61 ; 62 ; ALECTL0: ALE Lengthening Control Bit (BUSCON0.9): 63 _ALECTL0 EQU 0 ; see data sheet for description 64 ; 65 ; BUSACT0: Bus Active Control Bit (BUSCON0.10): 66 _BUSACT0 EQU 1 ; = 0 external bus disabled 67 ; = 1 external bus enabled 68 ; 69 ; RDYEN0: READY# Input Enable control bit (BUSCON0.12): 70 _RDYEN0 EQU 0 ; 0 = READY# function disabled (Reset Value) 71 ; ; 1 = READY# function enabled 72 ; 73 ; RDY_AS0: Synchronous / Asynchronous READY# Input (BUSCON0.3): 74 ; Note: This bit is only valid if _RDYEN0 == 1. 75 _RDY_AS0 EQU 0 ; 0 = synchronous READY# input 76 ; ; 1 = asynchronous READY# input 77 ; 78 ; CSREN0: Read Chip Select Enable bit (BUSCON0.14, only in some devices): 79 _CSREN0 EQU 0 ; 0 = CS0# is independent of read command (RD#) 80 ; ; 1 = CS0# is generated for the duration of read 81 ; 82 ; CSWEN0: Write Chip Select Enable bit (BUSCON0.15, only in some devices): 83 _CSWEN0 EQU 0 ; 0 = CS0# is independent of write command (WR#) 84 ; ; 1 = CS0# is generated for the duration of write 85 ; 86 ; XPERSHARE: XBUS Peripheral Share Mode Control (SYSCON.0) 87 _XPERSHARE EQU 0 ; 0 = External accesses to XBUS peripherals disabled 88 ; ; 1 = XBUS accessible via external BUS in hold mode 89 ; 90 ; VISIBLE: Visible Mode Control (SYSCON.1) 91 _VISIBLE EQU 0 ; 0 = Accesses to XBUS are done internally 92 ; ; 1 = XBUS accesses are made visible on external pins 93 ; 94 ; XPEN: XRAM & XBUS Peripheral Enable Control Bit (SYSCON.2) 95 _XPEN EQU 1 ; 0 = access to on-chip XRAM & XBUS disable => EXT.BUS 96 ; ; 1 = on-chip XRAM & XBUS is accessed 97 ; 98 ; BDRSTEN: Bidirectional Reset Enable Bit (SYSCON.3, only in some devices) 99 _BDRSTEN EQU 0 ; 0 = Pin RSTIN# is an input only 100 ; ; 1 = RSTIN# is pulled low during internal reset 101 ; 102 $SET (OWDDIS_ENABLE = 0); 0 = OWDDIS is set according to the inverted level 103 ; ; at pin RD\ duirng reset. 104 ; ; 1 = the following _OWDDIS value is 105 ; ; written to OWDDIS in the SYSCON register 106 ; OWDDIS: Oscillator Watchdog Disable Bit (SYSCON.4, only in some devices) 107 _OWDDIS EQU 0 ; 0 = the on-chip oscillator watchdog is enabled 108 ; ; 1 = the on-chip oscillator watchdog is disabled 109 ; 110 ; PWDCFG: Power Down Mode Configuration Bit (SYSCON.5, only in some devices) 111 _PWDCFG EQU 0 ; 0 = Power Down mode can be left via reset 112 ; ; 1 = Power Down mode left via ext. or RTC interrupt 113 ; 114 ; CSCFG: Chip Select Configuration Control (SYSCON.6, only in some devices) 115 _CSCFG EQU 0 ; 0 = Latched CS mode; CS signals are latch internally 116 ; ; 1 = Unlatched CS mode 117 ; 118 $SET (WRCFG_ENABLE = 0) ; 0 = WRCFG is set according to the level at 119 ; ; pin P0H.0 during reset. 120 ; ; 1 = the following _WRCFG value is 121 ; ; written to WRCFG in the SYSCON register 122 ; WRCFG: Write Configuration Control Bit (SYSCON.7): 123 _WRCFG EQU 1 ; 0 = Normal configuration of WR# and BHE# 124 ; ; 1 = WR# pin acts as WRL#, BHE# pin acts as WRH# 125 ; A166 MACRO ASSEMBLER START 01/12/05 22:15:52 PAGE 3 126 ; CLKEN: System Clock Output Enable bit (SYSCON.8): 127 _CLKEN EQU 0 ; 0 = disabled (Reset Value) 128 ; ; 1 = enabled 129 ; 130 ; BYTDIS: Byte High Enable pin control bit (SYSCON.9): 131 _BYTDIS EQU 0 ; 0 = enabled (Reset Value) 132 ; ; 1 = disabled 133 ; 134 ; ROMEN: Internal ROM Access Enable control bit (SYSCON.10): 135 _ROMEN EQU 0 ; 0 = Internal ROM disabled 136 ; 1 = Internal ROM enabled 137 ; 138 ; SGTDIS: Segmentation Disable control bit (SYSCON.11): $IF TINY _SGTDIS EQU 1 ; disable segmented mode for TINY model 141 $ELSE 142 _SGTDIS EQU 0 ; enable segmented mode (Reset Value) 143 $ENDIF 144 ; 145 ; ROMS1: ROM Segment Mapping Control Bit (SYSCON.12): 146 _ROMS1 EQU 0 ; _ROMS1 = 0 Internal ROM mapped to segment 0 147 ; ; _ROMS1 = 1 Internal ROM mapped to segment 1 148 ; 149 ; STKSZ: Maximum System Stack Size selection (SYSCON.13 .. SYSCON.15) 150 ; Defines the system stack space which is used by CALL/RET and PUSH/POP 151 ; instructions. The system stack space must be adjusted according the 152 ; actual requirements of the application. 153 $SET (STK_SIZE = 0) 154 ; System stack sizes: 155 ; 0 = 256 words (Reset Value) 156 ; 1 = 128 words 157 ; 2 = 64 words 158 ; 3 = 32 words 159 ; 4 = 512 words 160 ; 5 = not implemented 161 ; 6 = not implemented 162 ; 7 = no wrapping (entire internal RAM use as STACK, set size with SYSSZ) 163 ; If you have selected 7 for STK_SIZE, you can set the actual system stack size 164 ; with the following SSTSZ statement. 165 SSTSZ EQU 200H ; set System Stack Size to 200H Bytes 166 ; 167 ; USTSZ: User Stack Size Definition 168 ; Defines the user stack space available for automatics. This stack space is 169 ; accessed by R0. The user stack space must be adjusted according the actual 170 ; requirements of the application. 171 USTSZ EQU 1000H ; set User Stack Size to 1000H Bytes. 172 ; 173 ; WATCHDOG: Disable Hardware Watchdog 174 ; --- Set WATCHDOG = 1 to enable the Hardware watchdog 175 $SET (WATCHDOG = 0) 176 ; 177 ; 178 ; CLR_MEMORY: Disable Memory Zero Initialization of RAM area 179 ; --- Set CLR_MEMORY = 0 to disable memory zero initilization 180 $SET (CLR_MEMORY = 1) 181 ; 182 ; INIT_VARS: Disable Variable Initialization 183 ; --- Set INIT_VARS = 0 to disable variable initilization 184 $SET (INIT_VARS = 1) 185 ; 186 ; DPPUSE: Re-assign DPP registers 187 ; --- Set DPPUSE = 0 to reduce the code size of the startup code, if you 188 ; are not using the L166 DPPUSE directive. 189 $SET (DPPUSE = 0) 190 ; 191 ; DPP3USE: Use DPP3 register during variable initilization A166 MACRO ASSEMBLER START 01/12/05 22:15:52 PAGE 4 192 ; --- Set DPP3USE = 0 to disable the usage of DPP3 during initilization of 193 ; variables. This option might be required if you write 194 ; program parts that are reloaded during application 195 ; execution and increase code size of the startup code. 196 $SET (DPP3USE = 1) 197 ; 198 ;------------------------------------------------------------------------------ 199 ; Initialization for XPERCON register (available on some derivatives only 200 ; 201 ; INIT_XPERCON: Init XPERCON register available on some devices 202 ; --- Set INIT_XPERCON = 1 to initilize the XPERCON register 203 $SET (INIT_XPERCON = 0) 204 ; 205 ; --- XPERCON values 206 ; 207 ; V_CAN1: make CAN1 address range 0xEF00 .. 0xEFFF visible (XPERCON.0) 208 V_CAN1 EQU 1 ; 0 = CAN1 is not visible on the XBUS 209 ; ; 1 = CAN1 is visible on the XBUS (default) 210 ; 211 ; V_CAN2: make CAN2 address range 0xEE00 .. 0xEEFF visible (XPERCON.1) 212 V_CAN2 EQU 0 ; 0 = CAN2 is not visible on the XBUS (default) 213 ; ; 1 = CAN2 is visible on the XBUS 214 ; 215 ; V_XRAM2: make 2KB XRAM address range 0xE000 .. 0xE7FF visible (XPERCON.10) 216 V_XRAM2 EQU 1 ; 0 = 2KB XRAM is not visible on the XBUS 217 ; ; 1 = 2KB XRAM is visible on the XBUS (default) 218 ; 219 ; V_XRAM6: make 6KB XRAM address range 0xC000 .. 0xD7FF visible (XPERCON.11) 220 V_XRAM6 EQU 0 ; 0 = 6KB XRAM is not visible on the XBUS (default) 221 ; ; 1 = 6KB XRAM is visible on the XBUS 222 ; 223 ; V_XFLASH: make 4KB XFLASH address range 0x8000 .. 0x8FFF visible (XPERCON.14) 224 V_XFLASH EQU 0 ; 0 = 4KB XFLASH is not visible on the XBUS (default) 225 ; ; 1 = 4KB XFLASH is visible on the XBUS 226 ; 227 ;------------------------------------------------------------------------------ 228 ; 229 ; Initialization for SYSCON2 and SYSCON3 (available on some derivatives only) 230 ; Note: The SYSCON2 and SYSCON3 bits may be different in some derivatives. 231 ; Check the values carefully! 232 ; 233 ; ADVANCED_SYSCON: Init SYSCON2 and SYSCON3 register available on some devices 234 ; --- Set ADVANCE_SYSCON = 1 to initilize SYSCON2 and SYSCON3 235 $SET (ADVANCED_SYSCON = 0) 236 ; 237 ; --- SYSCON2 values 238 ; 239 ; PDCON: Power Down Control (during power down mode) (SYSCON2.4 .. SYSCON2.5) 240 PDCON EQU 0 ; 0 = RTC On, Ports On (default after Reset) 241 ; ; 1 = RTC On, Ports Off 242 ; ; 2 = RTC Off, Ports On 243 ; ; 3 = RTC Off, Ports Off 244 ; 245 ; RTS: RTC Clock Source (not affected by a reset) (SYSCON2.6) 246 RTS EQU 0 ; 0 = Main oscillator 247 ; ; 1 = Auxiliary oscillator (if available) 248 ; 249 ; SCS: SDD Clock Source (not affected by a reset) (SYSCON2.7) 250 SCS EQU 0 ; 0 = Main oscillator 251 ; ; 1 = Auxiliary oscillator (if available) 252 ; 253 ; CLKCON: Clock State Control (SYSCON2.8 .. SYSCON2.9) 254 CLKCON EQU 0 ; 0 = Running on configured basic frequency 255 ; ; 1 = Running on slow down frequency, PLL ON 256 ; ; 2 = Running on slow down frequency, PLL OFF 257 ; ; 3 = reserved A166 MACRO ASSEMBLER START 01/12/05 22:15:52 PAGE 5 258 ; 259 ; CLKREL: Reload Counter Value for Slowdown Devider (SYSCON2.10 .. SYSCON2.14) 260 CLKREL EQU 0 ; possible values are 0 .. 31 261 ; 262 ; 263 ; --- SYSCON3 values: disable on-chip peripherals 264 ; 265 ADCDIS EQU 0 ; 1 = disable Analog/Digital Converter (SYSCON3.0) 266 ASC0DIS EQU 0 ; 1 = disable UART ASC0 (SYSCON3.1) 267 SSCDIS EQU 0 ; 1 = disable Synchronus Serial Cnl SSC (SYSCON3.2) 268 GPTDIS EQU 0 ; 1 = disable Timer Block GPT (SYSCON3.3) 269 ; reserved (SYSCON3.4) 270 FMDIS EQU 0 ; 1 = disable on-chip Flash Memory Module (SYSCON3.5) 271 CC1DIS EQU 0 ; 1 = disable CAPCOM Unit 1 (SYSCON3.6) 272 CC2DIS EQU 0 ; 1 = disable CAPCOM Unit 2 (SYSCON3.7) 273 CC6DIS EQU 0 ; 1 = disable CAPCOM Unit 6 (SYSCON3.8) 274 PWMDIS EQU 0 ; 1 = disable Pulse Width Modulation Unit (SYSCON3.9) 275 ASC1DIS EQU 0 ; 1 = disable UART ASC1 (SYSCON3.10) 276 I2CDIS EQU 0 ; 1 = disable I2C Bus Module (SYSCON3.11) 277 ; ; reserved (SYSCON3.12) 278 CAN1DIS EQU 0 ; 1 = disable on-chip CAN Module 1 (SYSCON3.13) 279 CAN2DIS EQU 0 ; 1 = disable on-chip CAN Module 2 (SYSCON3.14) 280 PCDDIS EQU 0 ; 1 = disable Peripheral Clock Driver (SYSCON3.15) 281 ; 282 ;------------------------------------------------------------------------------ 283 ; 284 ; BUSCON1/ADDRSEL1 .. BUSCON4/ADDRSEL4 Initialization 285 ; =================================================== 286 ; 287 ; 288 ; BUSCON1/ADDRSEL1 289 ; --- Set BUSCON1 = 1 to initialize the BUSCON1/ADDRSEL1 registers 290 $SET (BUSCON1 = 1) 291 ; 292 ; Define the start address and the address range of Chip Select 1 (CS1#) 293 ; This values are used to set the ADDRSEL1 register 294 ; Set CS1# Start Address (default 100000H) 295 ; Set CS1# Range (default 1024K = 1MB) 296 ; 297 ; MCTC1: Memory Cycle Time (BUSCON1.0 .. BUSCON1.3): 298 ; Note: if RDYEN1 == 1 a maximum number of 7 waitstates can be selected 299 _MCTC1 EQU 2 ; Memory wait states is 1 (MCTC1 field = 0EH). 300 ; 301 ; RWDC1: Read/Write Signal Delay (BUSCON1.4): 302 _RWDC1 EQU 1 ; 0 = Delay Time 0.5 States 303 ; ; 1 = No Delay Time 0 States 304 ; 305 ; MTTC1: Memory Tri-state Time (BUSCON1.5): 306 _MTTC1 EQU 0 ; 0 = Delay Time 0.5 States 307 ; ; 1 = No Delay Time 0 States 308 ; 309 ; BTYP1: External Bus Configuration Control (BUSCON1.6 .. BUSCON1.7): 310 _BTYP1 EQU 2 ; 0 = 8 Bit Non Multiplexed 311 ; ; 1 = 8 Bit Multiplexed 312 ; ; 2 = 16 Bit Non Multiplexed 313 ; ; 3 = 16 Bit Multiplexed 314 ; 315 ; ALECTL1: ALE Lengthening Control Bit (BUSCON1.9): 316 _ALECTL1 EQU 0 ; see data sheet for description 317 ; 318 ; BUSACT1: Bus Active Control Bit (BUSCON1.10): 319 _BUSACT1 EQU 1 ; = 0 external (ADDRSEL1) bus disabled 320 ; = 1 external (ADDRSEL1) bus enabled 321 ; 322 ; RDYEN1: READY# Input Enable control bit (BUSCON1.12): 323 _RDYEN1 EQU 0 ; 0 = READY# function disabled A166 MACRO ASSEMBLER START 01/12/05 22:15:52 PAGE 6 324 ; ; 1 = READY# function enabled 325 ; 326 ; RDY_AS1: Synchronous / Asynchronous READY# Input (BUSCON1.3): 327 ; Note: This bit is only valid if _RDYEN1 == 1. 328 _RDY_AS1 EQU 0 ; 0 = synchronous READY# input 329 ; ; 1 = asynchronous READY# input 330 ; 331 ; CSREN1: Read Chip Select Enable bit (BUSCON1.14): 332 _CSREN1 EQU 0 ; 0 = CS1# is independent of read command (RD#) 333 ; ; 1 = CS1# is generated for the duration of read 334 ; 335 ; CSWEN1: Write Chip Select Enable bit (BUSCON1.15): 336 _CSWEN1 EQU 0 ; 0 = CS1# is independent of write command (WR#) 337 ; ; 1 = CS1# is generated for the duration of write 338 ; 339 ; 340 ; BUSCON2/ADDRSEL2 341 ; --- Set BUSCON2 = 1 to initialize the BUSCON2/ADDRSEL2 registers 342 $SET (BUSCON2 = 0) 343 ; 344 ; Define the start address and the address range of Chip Select 2 (CS2#) 345 ; This values are used to set the ADDRSEL2 register 346 ; Set CS2# Start Address (default 200000H) 347 ; Set CS2# Range (default 1024K = 1MB) 348 ; 349 ; MCTC2: Memory Cycle Time (BUSCON2.0 .. BUSCON2.3): 350 ; Note: if RDYEN2 == 1 a maximum number of 7 waitstates can be selected 351 _MCTC2 EQU 2 ; Memory wait states is 1 (MCTC2 field = 0EH). 352 ; 353 ; RWDC2: Read/Write Signal Delay (BUSCON2.4): 354 _RWDC2 EQU 1 ; 0 = Delay Time 0.5 States 355 ; ; 1 = No Delay Time 0 States 356 ; 357 ; MTTC2: Memory Tri-state Time (BUSCON2.5): 358 _MTTC2 EQU 0 ; 0 = Delay Time 0.5 States 359 ; ; 1 = No Delay Time 0 States 360 ; 361 ; BTYP2: External Bus Configuration Control (BUSCON2.6 .. BUSCON2.7): 362 _BTYP2 EQU 2 ; 0 = 8 Bit Non Multiplexed 363 ; ; 1 = 8 Bit Multiplexed 364 ; ; 2 = 16 Bit Non Multiplexed 365 ; ; 3 = 16 Bit Multiplexed 366 ; 367 ; ALECTL2: ALE Lengthening Control Bit (BUSCON2.9): 368 _ALECTL2 EQU 0 ; see data sheet for description 369 ; 370 ; BUSACT2: Bus Active Control Bit (BUSCON2.10): 371 _BUSACT2 EQU 1 ; = 0 external (ADDRSEL2) bus disabled 372 ; = 1 external (ADDRSEL2) bus enabled 373 ; 374 ; RDYEN2: READY# Input Enable control bit (BUSCON2.12): 375 _RDYEN2 EQU 0 ; 0 = READY# function disabled 376 ; ; 1 = READY# function enabled 377 ; 378 ; RDY_AS2: Synchronous / Asynchronous READY# Input (BUSCON2.3): 379 ; Note: This bit is only valid if _RDYEN2 == 1. 380 _RDY_AS2 EQU 0 ; 0 = synchronous READY# input 381 ; ; 1 = asynchronous READY# input 382 ; 383 ; CSREN2: Read Chip Select Enable bit (BUSCON2.14): 384 _CSREN2 EQU 0 ; 0 = CS2# is independent of read command (RD#) 385 ; ; 1 = CS2# is generated for the duration of read 386 ; 387 ; CSWEN2: Write Chip Select Enable bit (BUSCON2.15): 388 _CSWEN2 EQU 0 ; 0 = CS2# is independent of write command (WR#) 389 ; ; 1 = CS2# is generated for the duration of write A166 MACRO ASSEMBLER START 01/12/05 22:15:52 PAGE 7 390 ; 391 ; 392 ; BUSCON3/ADDRSEL3 393 ; --- Set BUSCON3 = 1 to initialize the BUSCON3/ADDRSEL3 registers 394 $SET (BUSCON3 = 0) 395 ; 396 ; Define the start address and the address range of Chip Select 3 (CS3#) 397 ; This values are used to set the ADDRSEL3 register 398 ; Set CS3# Start Address (default 300000H) 399 ; Set CS3# Range (default 1024K = 1MB) 400 ; 401 ; MCTC3: Memory Cycle Time (BUSCON3.0 .. BUSCON3.3): 402 ; Note: if RDYEN3 == 1 a maximum number of 7 waitstates can be selected 403 _MCTC3 EQU 2 ; Memory wait states is 1 (MCTC3 field = 0EH). 404 ; 405 ; RWDC3: Read/Write Signal Delay (BUSCON3.4): 406 _RWDC3 EQU 1 ; 0 = Delay Time 0.5 States 407 ; ; 1 = No Delay Time 0 States 408 ; 409 ; MTTC3: Memory Tri-state Time (BUSCON3.5): 410 _MTTC3 EQU 0 ; 0 = Delay Time 0.5 States 411 ; ; 1 = No Delay Time 0 States 412 ; 413 ; BTYP3: External Bus Configuration Control (BUSCON3.6 .. BUSCON3.7): 414 _BTYP3 EQU 2 ; 0 = 8 Bit Non Multiplexed 415 ; ; 1 = 8 Bit Multiplexed 416 ; ; 2 = 16 Bit Non Multiplexed 417 ; ; 3 = 16 Bit Multiplexed 418 ; 419 ; ALECTL3: ALE Lengthening Control Bit (BUSCON3.9): 420 _ALECTL3 EQU 0 ; see data sheet for description 421 ; 422 ; BUSACT3: Bus Active Control Bit (BUSCON3.10): 423 _BUSACT3 EQU 1 ; = 0 external (ADDRSEL3) bus disabled 424 ; = 1 external (ADDRSEL3) bus enabled 425 ; 426 ; RDYEN3: READY# Input Enable control bit (BUSCON3.12): 427 _RDYEN3 EQU 0 ; 0 = READY# function disabled 428 ; ; 1 = READY# function enabled 429 ; 430 ; RDY_AS3: Synchronous / Asynchronous READY# Input (BUSCON3.3): 431 ; Note: This bit is only valid if _RDYEN3 == 1. 432 _RDY_AS3 EQU 0 ; 0 = synchronous READY# input 433 ; ; 1 = asynchronous READY# input 434 ; 435 ; CSREN3: Read Chip Select Enable bit (BUSCON3.14): 436 _CSREN3 EQU 0 ; 0 = CS3# is independent of read command (RD#) 437 ; ; 1 = CS3# is generated for the duration of read 438 ; 439 ; CSWEN3: Write Chip Select Enable bit (BUSCON3.15): 440 _CSWEN3 EQU 0 ; 0 = CS3# is independent of write command (WR#) 441 ; ; 1 = CS3# is generated for the duration of write 442 ; 443 ; 444 ; BUSCON4/ADDRSEL4 445 ; --- Set BUSCON4 = 1 to initialize the BUSCON4/ADDRSEL4 registers 446 $SET (BUSCON4 = 0) 447 ; 448 ; Define the start address and the address range of Chip Select 4 (CS4#) 449 ; This values are used to set the ADDRSEL4 register 450 ; Set CS4# Start Address (default 400000H) 451 ; Set CS4# Range (default 1024K = 1MB) 452 ; 453 ; MCTC4: Memory Cycle Time (BUSCON4.0 .. BUSCON4.3): 454 ; Note: if RDYEN4 == 1 a maximum number of 7 waitstates can be selected 455 _MCTC4 EQU 2 ; Memory wait states is 1 (MCTC4 field = 0EH). A166 MACRO ASSEMBLER START 01/12/05 22:15:52 PAGE 8 456 ; 457 ; RWDC4: Read/Write Signal Delay (BUSCON4.4): 458 _RWDC4 EQU 1 ; 0 = Delay Time 0.5 States 459 ; ; 1 = No Delay Time 0 States 460 ; 461 ; MTTC4: Memory Tri-state Time (BUSCON4.5): 462 _MTTC4 EQU 0 ; 0 = Delay Time 0.5 States 463 ; ; 1 = No Delay Time 0 States 464 ; 465 ; BTYP4: External Bus Configuration Control (BUSCON4.6 .. BUSCON4.7): 466 _BTYP4 EQU 2 ; 0 = 8 Bit Non Multiplexed 467 ; ; 1 = 8 Bit Multiplexed 468 ; ; 2 = 16 Bit Non Multiplexed 469 ; ; 3 = 16 Bit Multiplexed 470 ; 471 ; ALECTL4: ALE Lengthening Control Bit (BUSCON4.9): 472 _ALECTL4 EQU 0 ; see data sheet for description 473 ; 474 ; BUSACT4: Bus Active Control Bit (BUSCON4.10): 475 _BUSACT4 EQU 1 ; = 0 external (ADDRSEL4) bus disabled 476 ; = 1 external (ADDRSEL4) bus enabled 477 ; 478 ; RDYEN4: READY# Input Enable control bit (BUSCON4.12): 479 _RDYEN4 EQU 0 ; 0 = READY# function disabled 480 ; ; 1 = READY# function enabled 481 ; 482 ; RDY_AS4: Synchronous / Asynchronous READY# Input (BUSCON4.3): 483 ; Note: This bit is only valid if _RDYEN4 == 1. 484 _RDY_AS4 EQU 0 ; 0 = synchronous READY# input 485 ; ; 1 = asynchronous READY# input 486 ; 487 ; CSREN4: Read Chip Select Enable bit (BUSCON4.14): 488 _CSREN4 EQU 0 ; 0 = CS4# is independent of read command (RD#) 489 ; ; 1 = CS4# is generated for the duration of read 490 ; 491 ; CSWEN4: Write Chip Select Enable bit (BUSCON4.15): 492 _CSWEN4 EQU 0 ; 0 = CS4# is independent of write command (WR#) 493 ; ; 1 = CS4# is generated for the duration of write 494 ; 495 ;------------------------------------------------------------------------------ 496 $IF TINY $SET (DPPUSE = 0) 499 $ENDIF 500 501 _STKSZ SET 0 502 _STKSZ1 SET 0 ; size is 512 Words 503 $IF (STK_SIZE = 0) 504 _STKSZ1 SET 1 ; size is 256 Words 505 $ENDIF $IF (STK_SIZE = 1) _STKSZ SET 1 _STKSZ1 SET 2 ; size is 128 Words 509 $ENDIF $IF (STK_SIZE = 2) _STKSZ SET 2 _STKSZ1 SET 3 ; size is 64 Words 513 $ENDIF $IF (STK_SIZE = 3) _STKSZ SET 3 _STKSZ1 SET 4 ; size is 32 Words 517 $ENDIF $IF (STK_SIZE = 4) _STKSZ SET 4 520 $ENDIF $IF (STK_SIZE = 5) A166 MACRO ASSEMBLER START 01/12/05 22:15:52 PAGE 9 _STKSZ SET 5 523 $ENDIF $IF (STK_SIZE = 6) _STKSZ SET 6 526 $ENDIF $IF (STK_SIZE = 7) _STKSZ SET 7 529 $ENDIF 530 531 532 $IF NOT TINY 533 ASSUME DPP3:SYSTEM 534 ASSUME DPP2:NDATA 535 $ENDIF 536 537 NAME ?C_STARTUP 538 PUBLIC ?C_STARTUP 539 540 $IF MEDIUM OR LARGE OR HLARGE 541 Model LIT 'FAR' $ELSE Model LIT 'NEAR' 544 $ENDIF 545 546 EXTRN main:FAR 547 548 PUBLIC ?C_USRSTKBOT 549 550 ?C_USERSTACK SECTION DATA PUBLIC 'NDATA' 551 $IF NOT TINY 552 NDATA DGROUP ?C_USERSTACK 553 $ENDIF 554 ?C_USRSTKBOT: 000000 555 DS USTSZ ; Size of User Stack 556 ?C_USERSTKTOP: 557 ?C_USERSTACK ENDS 558 559 ?C_MAINREGISTERS REGDEF R0 - R15 560 $IF (STK_SIZE = 7) ?C_SYSSTACK SECTION DATA PUBLIC 'IDATA' $IF NOT TINY SDATA DGROUP ?C_SYSSTACK $ENDIF _BOS: ; bottom of system stack DS SSTSZ ; Size of User Stack _TOS: ; top of system stack ?C_SYSSTACK ENDS 572 $ELSE 573 ; Setup Stack Overflow 574 _TOS EQU 0FC00H ; top of system stack 575 _BOS EQU _TOS - (1024 >> _STKSZ1) ; bottom of system stack 576 $ENDIF 577 578 PUBLIC ?C_SYSSTKBOT 579 ?C_SYSSTKBOT EQU _BOS 580 581 SSKDEF _STKSZ ; System stack size 582 583 ?C_STARTUP_CODE SECTION CODE 'ICODE' 584 585 586 ;------------------------------------------------------------------------------ 587 A166 MACRO ASSEMBLER START 01/12/05 22:15:52 PAGE 10 588 ; Special Function Register Addresses 589 SYSCON DEFR 0FF12H 590 BUSCON0 DEFR 0FF0CH 591 SP DEFR 0FE12H 592 STKOV DEFR 0FE14H 593 STKUN DEFR 0FE16H 594 P3 DEFR 0FFC4H 595 DP3 DEFR 0FFC6H 596 P5 DEFR 0FFA2H 597 BUSCON1 DEFR 0FF14H 598 BUSCON2 DEFR 0FF16H 599 BUSCON3 DEFR 0FF18H 600 BUSCON4 DEFR 0FF1AH 601 ADDRSEL1 DEFR 0FE18H 602 ADDRSEL2 DEFR 0FE1AH 603 ADDRSEL3 DEFR 0FE1CH 604 ADDRSEL4 DEFR 0FE1EH 605 SYSCON2 DEFR 0F1D0H 606 SYSCON3 DEFR 0F1D4H 607 608 609 610 611 ; --------------------------------------------------------------------- 612 ; Uncomment one of the following lines: 613 ?C_RESET PROC TASK C_STARTUP INTNO RESET = 0 614 ; THE ABOVE LINE CREATES A RESET VECTOR AT 0000H TO 615 ; START PROGRAM EXECUTION (f.e. Software in Flash)!! 616 ; C_RESET PROC NEAR 617 ; THE ABOVE LINE DOES NOT CREATE ANY RESET VECTOR!! 618 ; PROGRAM EXECUTION HAS TO BE STARTED BY ANY MANUAL JUMP 619 ; (f.e. by bootstrap loader, GO command within monitor)!! 620 ; --------------------------------------------------------------------- 621 622 ?C_STARTUP: LABEL FAR 623 624 625 $IF (WATCHDOG = 0) 000000 A55AA5A5 626 DISWDT ; Disable watchdog timer 627 $ENDIF 628 $IF (INIT_XPERCON = 1) ; Improtant XPERCON must be set before SYSCON.XPEN is enabled XPERCON DEFR 0F024H V_XPERCON SET V_CAN1 OR (V_CAN2 << 1) OR (V_XRAM2 << 10) V_XPERCON SET V_XPERCON OR (V_XRAM6 << 11) OR (V_XFLASH << 14) EXTR #1 MOV XPERCON,#V_XPERCON 636 $ENDIF 637 638 BCON0L SET (_MTTC0 << 5) OR (_RWDC0 << 4) 639 BCON0L SET BCON0L OR ((NOT _MCTC0) AND 0FH) 640 BCON0L SET BCON0L AND (NOT (_RDYEN0 << 3)) 641 BCON0L SET BCON0L OR (_RDY_AS0 << 3) 642 BCON0H SET (_ALECTL0 << 1) OR (_RDYEN0 << 4) 643 BCON0H SET BCON0H OR (_CSREN0 << 6) OR (_CSWEN0 << 7) $IF (BTYP_ENABLE == 1) BCON0L SET BCON0L OR (_BTYP0 << 6) BCON0H SET BCON0H OR (_BUSACT0 << 2) 647 $ENDIF 648 649 $IF (BTYP_ENABLE == 0) 000004 0A863F3D 650 BFLDL BUSCON0,#03FH,#BCON0L 000008 1A8600D2 651 BFLDH BUSCON0,#0D2H,#BCON0H $ELSE BFLDL BUSCON0,#0FFH,#BCON0L A166 MACRO ASSEMBLER START 01/12/05 22:15:52 PAGE 11 BFLDH BUSCON0,#0D6H,#BCON0H 655 $ENDIF 656 SYS_BITS SET 0FF6FH 657 658 SYS_H SET (_STKSZ << 5) OR (_ROMS1 << 4) OR (_SGTDIS << 3) 659 SYS_H SET SYS_H OR (_ROMEN << 2) OR (_BYTDIS << 1) OR _CLKEN 660 SYS_L SET _XPERSHARE OR (_VISIBLE << 1) OR (_XPEN << 2) 661 SYS_L SET SYS_L OR (_BDRSTEN << 3) 662 SYS_L SET SYS_L OR (_PWDCFG << 5) OR (_CSCFG << 6) $IF (WRCFG_ENABLE == 1) SYS_L SET SYS_L OR (_WRCFG << 7) SYS_BITS SET SYS_BITS OR 00080H 666 $ENDIF $IF (OWDDIS_ENABLE == 1) SYS_L SET SYS_L OR (_OWDDIS << 4) SYS_BITS SET SYS_BITS OR 00010H 670 $ENDIF 671 ; Setup SYSCON Register 672 00000C 1A8900FF 673 BFLDH SYSCON,#HIGH SYS_BITS,#SYS_H 000010 0A896F04 674 BFLDL SYSCON,#LOW SYS_BITS,#SYS_L 675 ; $IF (ADVANCED_SYSCON = 1) SYS_2 SET (PDCON << 4) OR (RTS << 6) OR (SCS << 7) SYS_2 SET SYS_2 OR (CLKCON << 8) OR (CLKREL << 10) SYS_3 SET ADCDIS OR (ASC0DIS << 1) OR (SSCDIS << 2) SYS_3 SET SYS_3 OR (GPTDIS << 3) SYS_3 SET SYS_3 OR (FMDIS << 5) OR (CC1DIS << 6) OR (CC2DIS << 7) SYS_3 SET SYS_3 OR (CC6DIS << 8) OR (PWMDIS << 9) SYS_3 SET SYS_3 OR (ASC1DIS << 10) OR (I2CDIS << 11) SYS_3 SET SYS_3 OR (CAN1DIS << 13) OR (CAN2DIS << 14) SYS_3 SET SYS_3 OR (PCDDIS << 15) EXTR #2 MOV SYSCON2,#SYS_2 MOV SYSCON3,#SYS_3 691 $ENDIF 692 ; 693 694 $IF (BUSCON1 = 1) 695 BCON1 SET (_MTTC1 << 5) OR (_RWDC1 << 4) 696 BCON1 SET BCON1 OR ((NOT _MCTC1) AND 0FH) 697 BCON1 SET BCON1 AND (NOT (_RDYEN1 << 3)) 698 BCON1 SET BCON1 OR (_RDY_AS1 << 3) OR (_BTYP1 << 6) 699 BCON1 SET BCON1 OR (_ALECTL1 << 9) OR (_BUSACT1 << 10) 700 BCON1 SET BCON1 OR (_RDYEN1 << 12) OR (_CSREN1 << 14) 701 BCON1 SET BCON1 OR (_CSWEN1 << 15) 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 A166 MACRO ASSEMBLER START 01/12/05 22:15:52 PAGE 12 720 721 ADDR1 EQU 1008H 722 723 724 725 726 ;--------------------------------------------------------------- 727 ;--------------------------------------------------------------- 728 ;--------------------------------------------------------------- 729 730 731 rrspec_test: 732 ; If key pressed at startup, we start hopefully downloaded ramprog 000014 CC00 733 NOP 000016 CC00 734 NOP 735 ; normally rom 736 global rrspec_normal 737 rrspec_normal: 738 ; MOV ADDRSEL1,#ADDR1 739 ; MOV BUSCON1,#BCON1 740 000018 E60C0604 741 MOV ADDRSEL1,#0406H 742 ; MOV BUSCON1,#048EH 00001C E68AAE04 743 MOV BUSCON1,#04AEH 744 000020 EA900000 R 745 JMPA CC_NC,rrspec_end 746 747 748 global rrspec_startram 749 rrspec_startram: 750 ; For saverness, we test if ram is init at time 000024 CC00 751 NOP 000026 CC00 752 NOP 000028 F2F618FE 753 MOV R6,ADDRSEL1 00002C 4866 754 CMP R6,#0006H 755 ; If ram, we do nothing more 00002E EA200000 R 756 JMPA CC_EQ,rrspec_end 757 758 759 760 ; Otherwise, we are in rom now, and have to switch to ram. 761 ; -------------------------------------------------------- 762 ; In this case BUSCON1 is not initiated currently 763 ; So, we can set ADDRSEL1 to 0000 with size 256 kb 000032 E60C0600 764 MOV ADDRSEL1,#0006H 000036 E68A8E04 765 MOV BUSCON1,#048EH 766 ; Last command switch on the Xbus, so this is the critical moment 767 ; Next instructions should be ram now. 00003A CC00 768 NOP 00003C CC00 769 NOP 00003E CC00 770 NOP 771 772 rrspec_end: 000040 CC00 773 NOP 000042 CC00 774 NOP 000044 CC00 775 NOP 776 777 ;--------------------------------------------------------------- 778 ;--------------------------------------------------------------- 779 ;--------------------------------------------------------------- 780 ;ATTENTION - NEVER CHANGE THE STUFF BEFORE THIS POINT 781 ;FOR BASE, AND RAMAPPS THE CODE BEFORE MUST BE COMPLETELY IDENTICAL 782 ;--------------------------------------------------------------- 783 784 785 $ENDIF A166 MACRO ASSEMBLER START 01/12/05 22:15:52 PAGE 13 786 $IF (BUSCON2 = 1) BCON2 SET (_MTTC2 << 5) OR (_RWDC2 << 4) BCON2 SET BCON2 OR ((NOT _MCTC2) AND 0FH) BCON2 SET BCON2 AND (NOT (_RDYEN2 << 3)) BCON2 SET BCON2 OR (_RDY_AS2 << 3) OR (_BTYP2 << 6) BCON2 SET BCON2 OR (_ALECTL2 << 9) OR (_BUSACT2 << 10) BCON2 SET BCON2 OR (_RDYEN2 << 12) OR (_CSREN2 << 14) BCON2 SET BCON2 OR (_CSWEN2 << 15) ADDR2 EQU 2008H MOV ADDRSEL2,#ADDR2 MOV BUSCON2,#BCON2 818 $ENDIF 819 $IF (BUSCON3 = 1) BCON3 SET (_MTTC3 << 5) OR (_RWDC3 << 4) BCON3 SET BCON3 OR ((NOT _MCTC3) AND 0FH) BCON3 SET BCON3 AND (NOT (_RDYEN3 << 3)) BCON3 SET BCON3 OR (_RDY_AS3 << 3) OR (_BTYP3 << 6) BCON3 SET BCON3 OR (_ALECTL3 << 9) OR (_BUSACT3 << 10) BCON3 SET BCON3 OR (_RDYEN3 << 12) OR (_CSREN3 << 14) BCON3 SET BCON3 OR (_CSWEN3 << 15) ADDR3 EQU 3008H MOV ADDRSEL3,#ADDR3 MOV BUSCON3,#BCON3 851 $ENDIF A166 MACRO ASSEMBLER START 01/12/05 22:15:52 PAGE 14 852 $IF (BUSCON4 = 1) BCON4 SET (_MTTC4 << 5) OR (_RWDC4 << 4) BCON4 SET BCON4 OR ((NOT _MCTC4) AND 0FH) BCON4 SET BCON4 AND (NOT (_RDYEN4 << 3)) BCON4 SET BCON4 OR (_RDY_AS4 << 3) OR (_BTYP4 << 6) BCON4 SET BCON4 OR (_ALECTL4 << 9) OR (_BUSACT4 << 10) BCON4 SET BCON4 OR (_RDYEN4 << 12) OR (_CSREN4 << 14) BCON4 SET BCON4 OR (_CSWEN4 << 15) ADDR4 EQU 4008H MOV ADDRSEL4,#ADDR4 MOV BUSCON4,#BCON4 884 $ENDIF 885 886 887 $IF (STK_SIZE = 7) MOV STKUN,#0FFFEH ; AVOID STKUN TRAP MOV STKOV,#0H ; AVOID STKOV TRAP MOV SP,#DPP3:_TOS ; INITIALIZE STACK POINTER MOV STKUN,#DPP3:_TOS ; INITIALIZE STACK UNFL REGISTER MOV STKOV,#DPP3:(_BOS+6*2) ; INITIALIZE STACK OVFL REGISTER 894 $ELSE 000046 E60A0CFA 895 MOV STKOV,#(_BOS+6*2) ; INITIALIZE STACK OVFL REGISTER 896 $ENDIF 897 898 $IF NOT TINY 899 900 EXTRN ?C_PAGEDPP0 : DATA16 901 EXTRN ?C_PAGEDPP1 : DATA16 902 EXTRN ?C_PAGEDPP2 : DATA16 903 $IF (DPPUSE = 1) MOV DPP0,#?C_PAGEDPP0 ; INIT DPP0 VALUE 906 $ENDIF 00004A E6010000 E 907 MOV DPP1,#?C_PAGEDPP1 ; DEFAULT NEAR CONST PAGE 00004E E6020000 E 908 MOV DPP2,#?C_PAGEDPP2 ; DEFAULT NEAR DATA PAGE 909 910 $ENDIF 911 000052 E6080000 R 912 MOV CP,#?C_MAINREGISTERS 000056 B54AB5B5 913 EINIT 914 915 ;$IF NOT TINY 916 ; MOV R0,#DPP2:?C_USERSTKTOP 917 ;$ELSE A166 MACRO ASSEMBLER START 01/12/05 22:15:52 PAGE 15 00005A E6F00010 R 918 MOV R0,#?C_USERSTKTOP 919 ;$ENDIF 920 921 922 ;------------------------------------------------------------------------------ 923 ; 924 ; The following code is necessary to set RAM variables to 0 at start-up 925 ; (RESET) of the C application program. 926 ; 927 928 $IF (CLR_MEMORY = 1) 929 930 EXTRN ?C_CLRMEMSECSTART : WORD 931 Clr_Memory: $IF TINY MOV R8,#?C_CLRMEMSECSTART JMPR cc_Z,EndClear RepeatClear: $IF (WATCHDOG = 1) SRVWDT ; SERVICE WATCHDOG $ENDIF MOV R5,#0 MOV R2,[R8+] ; Count JMPR cc_Z,EndClear MOV R3,R2 MOV R4,[R8+] JBC R2.14,ClearNear ClearBit: MOV R3,R4 SHR R3,#3 BCLR R3.0 ADD R3,#0FD00H ; START OF BIT SPACE MOV R5,#1 SHL R5,R4 CPL R5 AND R5,[R3] MOV [R3],R5 ADD R4,#1 SUB R2,#1 JMPR cc_NZ,ClearBit JMPR cc_UC,RepeatClear ClearNear: $IF (WATCHDOG = 1) SRVWDT ; SERVICE WATCHDOG $ENDIF MOVB [R4],RL5 ADD R4,#1 SUB R2,#1 JMPR cc_NN,ClearNear JMPR cc_UC,RepeatClear 971 $ELSE 00005E E6F90000 E 972 MOV R9,#SEG (?C_CLRMEMSECSTART) 000062 E6F80000 E 973 MOV R8,#SOF (?C_CLRMEMSECSTART) 000066 F018 974 MOV R1,R8 000068 7019 975 OR R1,R9 00006A 2D29 976 JMPR cc_Z,EndClear 977 978 RepeatClear: $IF (WATCHDOG = 1) SRVWDT ; SERVICE WATCHDOG 981 $ENDIF 00006C E005 982 MOV R5,#0 00006E DC09 983 EXTS R9,#1 A166 MACRO ASSEMBLER START 01/12/05 22:15:52 PAGE 16 000070 9828 984 MOV R2,[R8+] ; Count 000072 2D25 985 JMPR cc_Z,EndClear 000074 F032 986 MOV R3,R2 000076 DC09 987 EXTS R9,#1 000078 9848 988 MOV R4,[R8+] 00007A AAF21BE0 989 JBC R2.14,ClearNear 00007E AAF20EF0 990 JBC R2.15,ClearFar 991 000082 F034 992 ClearBit: MOV R3,R4 000084 7C33 993 SHR R3,#3 000086 0EF3 994 BCLR R3.0 000088 06F300FD 995 ADD R3,#0FD00H ; START OF BIT SPACE 00008C E015 996 MOV R5,#1 00008E 4C54 997 SHL R5,R4 000090 9150 998 CPL R5 000092 685B 999 AND R5,[R3] 000094 B853 1000 MOV [R3],R5 000096 0841 1001 ADD R4,#1 000098 2821 1002 SUB R2,#1 00009A 3DF3 1003 JMPR cc_NZ,ClearBit 00009C 0DE7 1004 JMPR cc_UC,RepeatClear 1005 00009E DC09 1006 ClearFar: EXTS R9,#1 0000A0 9838 1007 MOV R3,[R8+] 1008 RepClearFar: $IF (WATCHDOG = 1) SRVWDT ; SERVICE WATCHDOG 1011 $ENDIF 0000A2 DC44 1012 EXTP R4,#1 0000A4 B9A3 1013 MOVB [R3],RL5 0000A6 0831 1014 ADD R3,#1 0000A8 1840 1015 ADDC R4,#0 0000AA 76F300C0 1016 OR R3,#0C000H 0000AE 2821 1017 SUB R2,#1 0000B0 7DF8 1018 JMPR cc_NN,RepClearFar 0000B2 0DDC 1019 JMPR cc_UC,RepeatClear 1020 1021 ClearNear: $IF (WATCHDOG = 1) SRVWDT ; SERVICE WATCHDOG 1024 $ENDIF 0000B4 B9A4 1025 MOVB [R4],RL5 0000B6 0841 1026 ADD R4,#1 0000B8 2821 1027 SUB R2,#1 0000BA 7DFC 1028 JMPR cc_NN,ClearNear 0000BC 0DD7 1029 JMPR cc_UC,RepeatClear 1030 $ENDIF 1031 1032 EndClear: 1033 1034 $ENDIF 1035 1036 ;------------------------------------------------------------------------------ 1037 ; 1038 ; The following code is necessary, if the application program contains 1039 ; initialized variables at file level. 1040 ; 1041 1042 $IF (INIT_VARS = 1) ; ********************************************************* 1043 1044 EXTRN ?C_INITSECSTART : WORD 1045 Init_Vars: $IF TINY ; ******************************************************************** MOV R8,#?C_INITSECSTART RepeatInit: $IF (WATCHDOG = 1) A166 MACRO ASSEMBLER START 01/12/05 22:15:52 PAGE 17 SRVWDT ; SERVICE WATCHDOG $ENDIF MOV R2,[R8+] JMPR cc_Z,EndInit JBC R2.15,InitBit MOV R4,R2 AND R2,#3FFFH JMPR cc_NZ,LenLoad MOV R4,#0 MOV R2,[R8+] LenLoad: MOV R3,[R8+] CopyInitVal: MOVB [R3],[R8+] $IF (WATCHDOG = 1) SRVWDT ; SERVICE WATCHDOG $ENDIF ADD R3,#1 SUB R2,#1 JMPR cc_NZ,CopyInitVal JNB R8.0,RepeatInit ADD R8,#1 JMPR cc_UC,RepeatInit InitBit: MOVBZ R3,RL2 SHL R3,#1 OR R3,#0FD00H ; START OF BIT SPACE MOV R4,#1 MOVB RL5,RH2 SHL R4,R5 ; CALCULATE BIT MASK JB R2.7,SetBit CPL R4 ; CLEAR BIT AND R4,[R3] JMPR cc_UC,StoreBit SetBit: OR R4,[R3] ; SET BIT StoreBit: MOV [R3],R4 JMPR cc_UC,RepeatInit EndInit: 1088 $ELSE ; $IF TINY ************************************************************** 0000BE E6F90000 E 1089 MOV R9,#SEG (?C_INITSECSTART) 0000C2 E6F80000 E 1090 MOV R8,#SOF (?C_INITSECSTART) 1091 $IF (DPP3USE = 1) ; *********************************************************** 1092 RepeatInit: $IF (WATCHDOG = 1) SRVWDT ; SERVICE WATCHDOG 1095 $ENDIF 0000C6 E6030300 1096 MOV DPP3,#3 0000CA DC09 1097 EXTS R9,#1 0000CC A828 1098 MOV R2,[R8] 0000CE 2D3C 1099 JMPR cc_Z,EndInit 0000D0 0882 1100 ADD R8,#2 0000D2 1890 1101 ADDC R9,#0 0000D4 AAF229F0 1102 JBC R2.15,InitBit 0000D8 F042 1103 MOV R4,R2 0000DA 66F2FF3F 1104 AND R2,#3FFFH 0000DE 3D05 1105 JMPR cc_NZ,LenLoad 0000E0 E004 1106 MOV R4,#0 0000E2 DC09 1107 EXTS R9,#1 0000E4 A828 1108 MOV R2,[R8] 0000E6 0882 1109 ADD R8,#2 0000E8 1890 1110 ADDC R9,#0 0000EA DC09 1111 LenLoad: EXTS R9,#1 0000EC A838 1112 MOV R3,[R8] 0000EE 0882 1113 ADD R8,#2 0000F0 1890 1114 ADDC R9,#0 0000F2 8AF406E0 1115 JB R4.14,CopyInitVal A166 MACRO ASSEMBLER START 01/12/05 22:15:52 PAGE 18 0000F6 F6F306FE 1116 MOV DPP3,R3 0000FA DC09 1117 EXTS R9,#1 0000FC A838 1118 MOV R3,[R8] 0000FE 0882 1119 ADD R8,#2 000100 1890 1120 ADDC R9,#0 000102 DC09 1121 CopyInitVal: EXTS R9,#1 000104 A9A8 1122 MOVB RL5,[R8] 000106 0881 1123 ADD R8,#1 000108 1890 1124 ADDC R9,#0 00010A B9A3 1125 MOVB [R3],RL5 00010C 0831 1126 ADD R3,#1 00010E 8AF406E0 1127 JB R4.14,NoDPP3Adj 000112 8AF304E0 1128 JB R3.14,NoDPP3Adj 000116 06030100 1129 ADD DPP3,#1 00011A 76F300C0 1130 OR R3,#0C000H ; SET DPP3 Bits 1131 NoDPP3Adj: $IF (WATCHDOG = 1) SRVWDT ; SERVICE WATCHDOG 1134 $ENDIF 00011E 2821 1135 SUB R2,#1 000120 3DF0 1136 JMPR cc_NZ,CopyInitVal 000122 9AF8D000 1137 JNB R8.0,RepeatInit 000126 0881 1138 ADD R8,#1 000128 0DCE 1139 JMPR cc_UC,RepeatInit 1140 00012A C043 1141 InitBit: MOVBZ R3,RL2 00012C 5C13 1142 SHL R3,#1 00012E 76F300FD 1143 OR R3,#0FD00H ; START OF BIT SPACE 000132 E014 1144 MOV R4,#1 000134 F1A5 1145 MOVB RL5,RH2 000136 4C45 1146 SHL R4,R5 ; CALCULATE BIT MASK 000138 8AF20370 1147 JB R2.7,SetBit 00013C 9140 1148 CPL R4 ; CLEAR BIT 00013E 684B 1149 AND R4,[R3] 000140 0D01 1150 JMPR cc_UC,StoreBit 000142 784B 1151 SetBit: OR R4,[R3] ; SET BIT 000144 B843 1152 StoreBit: MOV [R3],R4 000146 0DBF 1153 JMPR cc_UC,RepeatInit 1154 $ELSE ; block IF (DPP3USE = 1) ************************************************ RepeatInit: $IF (WATCHDOG = 1) SRVWDT ; SERVICE WATCHDOG $ENDIF EXTS R9,#1 MOV R2,[R8] JMPR cc_Z,EndInit ADD R8,#2 ADDC R9,#0 JBC R2.15,InitBit MOV R4,R2 AND R2,#3FFFH JMPR cc_NZ,LenLoad MOV R4,#0 EXTS R9,#1 MOV R2,[R8] ADD R8,#2 ADDC R9,#0 LenLoad: EXTS R9,#1 MOV R3,[R8] ADD R8,#2 ADDC R9,#0 JB R4.14,CopyNearVal MOV R6,R3 EXTS R9,#1 MOV R3,[R8] A166 MACRO ASSEMBLER START 01/12/05 22:15:52 PAGE 19 ADD R8,#2 ADDC R9,#0 CopyInitVal: OR R6,#0C000H EXTP R6,#1 MOV [R3],RL5 ADD R3,#1 ADDC R6,#0 $IF (WATCHDOG = 1) SRVWDT ; SERVICE WATCHDOG $ENDIF SUB R2,#1 JMPR cc_NZ,CopyInitVal JMPR cc_UC,CopyInitDone CopyNearVal: EXTS R9,#1 MOVB RL5,[R8] ADD R8,#1 ADDC R9,#0 MOVB [R3],RL5 ADD R3,#1 $IF (WATCHDOG = 1) SRVWDT ; SERVICE WATCHDOG $ENDIF SUB R2,#1 JMPR cc_NZ,CopyNearVal CopyInitDone: JNB R8.0,RepeatInit ADD R8,#1 JMPR cc_UC,RepeatInit InitBit: MOVBZ R3,RL2 SHL R3,#1 OR R3,#0FD00H ; START OF BIT SPACE MOV R4,#1 MOVB RL5,RH2 SHL R4,R5 ; CALCULATE BIT MASK JB R2.7,SetBit CPL R4 ; CLEAR BIT AND R4,[R3] JMPR cc_UC,StoreBit SetBit: OR R4,[R3] ; SET BIT StoreBit: MOV [R3],R4 JMPR cc_UC,RepeatInit 1225 $ENDIF ; close block IF (DPP3USE = 1) **************************************** 1226 1227 EndInit: 1228 1229 $ENDIF ; close block $IF TINY ************************************************ 1230 1231 $ENDIF ; close $IF (INIT_VARS = 1) ******************************************* 1232 1233 ;------------------------------------------------------------------------------ 1234 $IF TINY JMP main 1237 $ELSE 000148 FA000000 E 1238 JMP FAR main 1239 $ENDIF 1240 1241 ?C_RESET ENDP 1242 1243 1244 ?C_STARTUP_CODE ENDS 1245 1246 $IF (INIT_VARS = 1) 1247 EXTERN ?C_ENDINIT:WORD A166 MACRO ASSEMBLER START 01/12/05 22:15:52 PAGE 20 1248 $ENDIF 1249 1250 END A166 MACRO ASSEMBLER START 01/12/05 22:15:52 PAGE 21 SYMBOL TABLE LISTING ------ ----- ------- N A M E TYPE VALUE I ATTRIBUTES ?C_CLRMEMSECSTART. WORD ---- EXT ?C_ENDINIT . . . . WORD ---- EXT ?C_INITSECSTART. . WORD ---- EXT ?C_MAINREGISTERS . ---- ---- REGBANK ?C_PAGEDPP0. . . . DAT16 ---- EXT ?C_PAGEDPP1. . . . DAT16 ---- EXT ?C_PAGEDPP2. . . . DAT16 ---- EXT ?C_RESET . . . . . FAR 0H R SEC=?C_STARTUP_CODE ?C_STARTUP . . . . FAR 0H R PUB SEC=?C_STARTUP_CODE ?C_STARTUP_CODE. . ---- ---- SECTION ?C_SYSSTKBOT . . . DAT16 FA00H A PUB ?C_USERSTACK . . . ---- ---- SECTION ?C_USERSTKTOP. . . BYTE 1000H R SEC=?C_USERSTACK ?C_USRSTKBOT . . . BYTE 0H R PUB SEC=?C_USERSTACK ADCDIS . . . . . . DATA3 0H A ADDR1. . . . . . . DAT16 1008H A ADDRSEL1 . . . . . WORD FE18H A SFR ADDRSEL2 . . . . . WORD FE1AH A SFR ADDRSEL3 . . . . . WORD FE1CH A SFR ADDRSEL4 . . . . . WORD FE1EH A SFR ASC0DIS. . . . . . DATA3 0H A ASC1DIS. . . . . . DATA3 0H A BCON0H . . . . . . DATA3 0H A BCON0L . . . . . . DATA8 3DH A BCON1. . . . . . . DAT16 49DH A BUSCON0. . . . . . WORD FF0CH A SFR BUSCON1. . . . . . WORD FF14H A SFR BUSCON2. . . . . . WORD FF16H A SFR BUSCON3. . . . . . WORD FF18H A SFR BUSCON4. . . . . . WORD FF1AH A SFR CAN1DIS. . . . . . DATA3 0H A CAN2DIS. . . . . . DATA3 0H A CC1DIS . . . . . . DATA3 0H A CC2DIS . . . . . . DATA3 0H A CC6DIS . . . . . . DATA3 0H A CLKCON . . . . . . DATA3 0H A CLKREL . . . . . . DATA3 0H A CP . . . . . . . . WORD FE10H A SFR C_STARTUP. . . . . ---- ---- ClearBit . . . . . NEAR 82H R SEC=?C_STARTUP_CODE ClearFar . . . . . NEAR 9EH R SEC=?C_STARTUP_CODE ClearNear. . . . . NEAR B4H R SEC=?C_STARTUP_CODE Clr_Memory . . . . NEAR 5EH R SEC=?C_STARTUP_CODE CopyInitVal. . . . NEAR 102H R SEC=?C_STARTUP_CODE DP3. . . . . . . . WORD FFC6H A SFR DPP1 . . . . . . . WORD FE02H A SFR DPP2 . . . . . . . WORD FE04H A SFR DPP3 . . . . . . . WORD FE06H A SFR EndClear . . . . . NEAR BEH R SEC=?C_STARTUP_CODE EndInit. . . . . . NEAR 148H R SEC=?C_STARTUP_CODE FMDIS. . . . . . . DATA3 0H A GPTDIS . . . . . . DATA3 0H A I2CDIS . . . . . . DATA3 0H A InitBit. . . . . . NEAR 12AH R SEC=?C_STARTUP_CODE Init_Vars. . . . . NEAR BEH R SEC=?C_STARTUP_CODE LenLoad. . . . . . NEAR EAH R SEC=?C_STARTUP_CODE Model. . . . . . . LIT "FAR" NDATA. . . . . . . ---- ---- GROUP NoDPP3Adj. . . . . NEAR 11EH R SEC=?C_STARTUP_CODE P3 . . . . . . . . WORD FFC4H A SFR A166 MACRO ASSEMBLER START 01/12/05 22:15:52 PAGE 22 P5 . . . . . . . . WORD FFA2H A SFR PCDDIS . . . . . . DATA3 0H A PDCON. . . . . . . DATA3 0H A PWMDIS . . . . . . DATA3 0H A RESET. . . . . . . INTNO 0000H RTS. . . . . . . . DATA3 0H A RepClearFar. . . . NEAR A2H R SEC=?C_STARTUP_CODE RepeatClear. . . . NEAR 6CH R SEC=?C_STARTUP_CODE RepeatInit . . . . NEAR C6H R SEC=?C_STARTUP_CODE SCS. . . . . . . . DATA3 0H A SP . . . . . . . . WORD FE12H A SFR SSCDIS . . . . . . DATA3 0H A SSTSZ. . . . . . . DAT16 200H A STKOV. . . . . . . WORD FE14H A SFR STKUN. . . . . . . WORD FE16H A SFR SYSCON . . . . . . WORD FF12H A SFR SYSCON2. . . . . . WORD F1D0H A ESF SYSCON3. . . . . . WORD F1D4H A ESF SYS_BITS . . . . . DAT16 FF6FH A SYS_H. . . . . . . DATA3 0H A SYS_L. . . . . . . DATA3 4H A SetBit . . . . . . NEAR 142H R SEC=?C_STARTUP_CODE StoreBit . . . . . NEAR 144H R SEC=?C_STARTUP_CODE USTSZ. . . . . . . DAT16 1000H A V_CAN1 . . . . . . DATA3 1H A V_CAN2 . . . . . . DATA3 0H A V_XFLASH . . . . . DATA3 0H A V_XRAM2. . . . . . DATA3 1H A V_XRAM6. . . . . . DATA3 0H A _ALECTL0 . . . . . DATA3 0H A _ALECTL1 . . . . . DATA3 0H A _ALECTL2 . . . . . DATA3 0H A _ALECTL3 . . . . . DATA3 0H A _ALECTL4 . . . . . DATA3 0H A _BDRSTEN . . . . . DATA3 0H A _BOS . . . . . . . DAT16 FA00H A _BTYP0 . . . . . . DATA3 2H A _BTYP1 . . . . . . DATA3 2H A _BTYP2 . . . . . . DATA3 2H A _BTYP3 . . . . . . DATA3 2H A _BTYP4 . . . . . . DATA3 2H A _BUSACT0 . . . . . DATA3 1H A _BUSACT1 . . . . . DATA3 1H A _BUSACT2 . . . . . DATA3 1H A _BUSACT3 . . . . . DATA3 1H A _BUSACT4 . . . . . DATA3 1H A _BYTDIS. . . . . . DATA3 0H A _CLKEN . . . . . . DATA3 0H A _CSCFG . . . . . . DATA3 0H A _CSREN0. . . . . . DATA3 0H A _CSREN1. . . . . . DATA3 0H A _CSREN2. . . . . . DATA3 0H A _CSREN3. . . . . . DATA3 0H A _CSREN4. . . . . . DATA3 0H A _CSWEN0. . . . . . DATA3 0H A _CSWEN1. . . . . . DATA3 0H A _CSWEN2. . . . . . DATA3 0H A _CSWEN3. . . . . . DATA3 0H A _CSWEN4. . . . . . DATA3 0H A _MCTC0 . . . . . . DATA3 2H A _MCTC1 . . . . . . DATA3 2H A _MCTC2 . . . . . . DATA3 2H A _MCTC3 . . . . . . DATA3 2H A _MCTC4 . . . . . . DATA3 2H A _MTTC0 . . . . . . DATA3 1H A _MTTC1 . . . . . . DATA3 0H A A166 MACRO ASSEMBLER START 01/12/05 22:15:52 PAGE 23 _MTTC2 . . . . . . DATA3 0H A _MTTC3 . . . . . . DATA3 0H A _MTTC4 . . . . . . DATA3 0H A _OWDDIS. . . . . . DATA3 0H A _PWDCFG. . . . . . DATA3 0H A _RDYEN0. . . . . . DATA3 0H A _RDYEN1. . . . . . DATA3 0H A _RDYEN2. . . . . . DATA3 0H A _RDYEN3. . . . . . DATA3 0H A _RDYEN4. . . . . . DATA3 0H A _RDY_AS0 . . . . . DATA3 0H A _RDY_AS1 . . . . . DATA3 0H A _RDY_AS2 . . . . . DATA3 0H A _RDY_AS3 . . . . . DATA3 0H A _RDY_AS4 . . . . . DATA3 0H A _ROMEN . . . . . . DATA3 0H A _ROMS1 . . . . . . DATA3 0H A _RWDC0 . . . . . . DATA3 1H A _RWDC1 . . . . . . DATA3 1H A _RWDC2 . . . . . . DATA3 1H A _RWDC3 . . . . . . DATA3 1H A _RWDC4 . . . . . . DATA3 1H A _SGTDIS. . . . . . DATA3 0H A _STKSZ . . . . . . DATA3 0H A _STKSZ1. . . . . . DATA3 1H A _TOS . . . . . . . DAT16 FC00H A _VISIBLE . . . . . DATA3 0H A _WRCFG . . . . . . DATA3 1H A _XPEN. . . . . . . DATA3 1H A _XPERSHARE . . . . DATA3 0H A main . . . . . . . FAR ---- EXT rrspec_end . . . . NEAR 40H R SEC=?C_STARTUP_CODE rrspec_normal. . . NEAR 18H R GLB SEC=?C_STARTUP_CODE rrspec_startram. . NEAR 24H R GLB SEC=?C_STARTUP_CODE rrspec_test. . . . NEAR 14H R SEC=?C_STARTUP_CODE ASSEMBLY COMPLETE. 0 WARNING(S), 0 ERROR(S)