A166 MACRO ASSEMBLER START 08/28/03 20:15:47 PAGE 1 DOS MACRO ASSEMBLER A166 V3.10 OBJECT MODULE PLACED IN START.OBJ ASSEMBLER INVOKED BY: C:\C166\BIN\A166.EXE START.A66 CASE MOD167 SEGMENTED SET(LARGE) LOC OBJ LINE SOURCE 1 $MOD167 ; Define C167 mode 2 ; 3 ;------------------------------------------------------------------------------ 4 ; This file is part of the C166 Compiler package 5 ; Copyright KEIL ELEKTRONIK GmbH 1993-1999 6 ; Version 4.01 7 ; Modified by Phytec 12.08.1999 8 ;------------------------------------------------------------------------------ 9 ; START167.A66: This code is executed after processor reset and provides the 10 ; startup sequence for the extended 166 architecture CPU's. 11 ; (i.e. C167/C165/C164/C163/C161, ST10-262 ect.) 12 ; 13 ; To translate this file use A166 with the following invocation: 14 ; 15 ; A166 START167.A66 SET () 16 ; 17 ; determines the memory model and can be one of the following: 18 ; TINY, SMALL, COMPACT, HCOMPACT, MEDIUM, LARGE or HLARGE 19 ; 20 ; Example: A166 START167.A66 SET (SMALL) 21 ; 22 ; To link the modified START167.OBJ file to your application use the following 23 ; L166 invocation: 24 ; 25 ; L166 , START167.OBJ 26 ; 27 ;------------------------------------------------------------------------------ 28 ; Setup model-dependend Assembler controls 29 $CASE 30 $IF NOT TINY 31 $SEGMENTED 32 $ENDIF 33 ;------------------------------------------------------------------------------ 34 ; 35 ; Definitions for BUSCON0 and SYSCON Register: 36 ; -------------------------------------------- 37 ; 38 ; MCTC0: Memory Cycle Time (BUSCON0.0 .. BUSCON0.3): 39 ; Note: if RDYEN0 == 1 a maximum number of 7 waitstates can be selected 40 _MCTC0 EQU 2 ; Memory wait states is 1 (MCTC0 field = 0EH). 41 ; ; (Reset Value = 15 additional state times) 42 ; 43 ; RWDC0: Read/Write Signal Delay (BUSCON0.4): 44 _RWDC0 EQU 1 ; 0 = Delay Time 0.5 States (Reset Value) 45 ; ; 1 = No Delay Time 0 States 46 ; 47 ; MTTC0: Memory Tri-state Time (BUSCON0.5): 48 _MTTC0 EQU 0 ; 0 = Delay Time 0.5 States (Reset Value) 49 ; ; 1 = No Delay Time 0 States 50 ; 51 $SET (BTYP_ENABLE = 0) ; 0 = BTYP0 and BUSACT0 is set according to the level 52 ; at pins P0L.6, P0L.7, and EA# during reset. 53 ; 1 = the following _BTYP0 and _BUSACT0 values are 54 ; written to BTYP0 and BUSACT0 55 ; 56 ; BTYP0: External Bus Configuration Control (BUSCON0.6 .. BUSCON0.7): 57 _BTYP0 EQU 2 ; 0 = 8 Bit Non Multiplexed 58 ; ; 1 = 8 Bit Multiplexed 59 ; ; 2 = 16 Bit Non Multiplexed A166 MACRO ASSEMBLER START 08/28/03 20:15:47 PAGE 2 60 ; ; 3 = 16 Bit Multiplexed 61 ; 62 ; ALECTL0: ALE Lengthening Control Bit (BUSCON0.9): 63 _ALECTL0 EQU 0 ; see data sheet for description 64 ; 65 ; BUSACT0: Bus Active Control Bit (BUSCON0.10): 66 _BUSACT0 EQU 1 ; = 0 external bus disabled 67 ; = 1 external bus enabled 68 ; 69 ; RDYEN0: READY# Input Enable control bit (BUSCON0.12): 70 _RDYEN0 EQU 0 ; 0 = READY# function disabled (Reset Value) 71 ; ; 1 = READY# function enabled 72 ; 73 ; RDY_AS0: Synchronous / Asynchronous READY# Input (BUSCON0.3): 74 ; Note: This bit is only valid if _RDYEN0 == 1. 75 _RDY_AS0 EQU 0 ; 0 = synchronous READY# input 76 ; ; 1 = asynchronous READY# input 77 ; 78 ; CSREN0: Read Chip Select Enable bit (BUSCON0.14, only in some devices): 79 _CSREN0 EQU 0 ; 0 = CS0# is independent of read command (RD#) 80 ; ; 1 = CS0# is generated for the duration of read 81 ; 82 ; CSWEN0: Write Chip Select Enable bit (BUSCON0.15, only in some devices): 83 _CSWEN0 EQU 0 ; 0 = CS0# is independent of write command (WR#) 84 ; ; 1 = CS0# is generated for the duration of write 85 ; 86 ; XPERSHARE: XBUS Peripheral Share Mode Control (SYSCON.0) 87 _XPERSHARE EQU 0 ; 0 = External accesses to XBUS peripherals disabled 88 ; ; 1 = XBUS accessible via external BUS in hold mode 89 ; 90 ; VISIBLE: Visible Mode Control (SYSCON.1) 91 _VISIBLE EQU 0 ; 0 = Accesses to XBUS are done internally 92 ; ; 1 = XBUS accesses are made visible on external pins 93 ; 94 ; XPEN: XRAM & XBUS Peripheral Enable Control Bit (SYSCON.2) 95 _XPEN EQU 1 ; 0 = access to on-chip XRAM & XBUS disable => EXT.BUS 96 ; ; 1 = on-chip XRAM & XBUS is accessed 97 ; 98 ; BDRSTEN: Bidirectional Reset Enable Bit (SYSCON.3, only in some devices) 99 _BDRSTEN EQU 0 ; 0 = Pin RSTIN# is an input only 100 ; ; 1 = RSTIN# is pulled low during internal reset 101 ; 102 $SET (OWDDIS_ENABLE = 0); 0 = OWDDIS is set according to the inverted level 103 ; ; at pin RD\ duirng reset. 104 ; ; 1 = the following _OWDDIS value is 105 ; ; written to OWDDIS in the SYSCON register 106 ; OWDDIS: Oscillator Watchdog Disable Bit (SYSCON.4, only in some devices) 107 _OWDDIS EQU 0 ; 0 = the on-chip oscillator watchdog is enabled 108 ; ; 1 = the on-chip oscillator watchdog is disabled 109 ; 110 ; PWDCFG: Power Down Mode Configuration Bit (SYSCON.5, only in some devices) 111 _PWDCFG EQU 0 ; 0 = Power Down mode can be left via reset 112 ; ; 1 = Power Down mode left via ext. or RTC interrupt 113 ; 114 ; CSCFG: Chip Select Configuration Control (SYSCON.6, only in some devices) 115 _CSCFG EQU 0 ; 0 = Latched CS mode; CS signals are latch internally 116 ; ; 1 = Unlatched CS mode 117 ; 118 $SET (WRCFG_ENABLE = 0) ; 0 = WRCFG is set according to the level at 119 ; ; pin P0H.0 during reset. 120 ; ; 1 = the following _WRCFG value is 121 ; ; written to WRCFG in the SYSCON register 122 ; WRCFG: Write Configuration Control Bit (SYSCON.7): 123 _WRCFG EQU 1 ; 0 = Normal configuration of WR# and BHE# 124 ; ; 1 = WR# pin acts as WRL#, BHE# pin acts as WRH# 125 ; A166 MACRO ASSEMBLER START 08/28/03 20:15:47 PAGE 3 126 ; CLKEN: System Clock Output Enable bit (SYSCON.8): 127 _CLKEN EQU 0 ; 0 = disabled (Reset Value) 128 ; ; 1 = enabled 129 ; 130 ; BYTDIS: Byte High Enable pin control bit (SYSCON.9): 131 _BYTDIS EQU 0 ; 0 = enabled (Reset Value) 132 ; ; 1 = disabled 133 ; 134 ; ROMEN: Internal ROM Access Enable control bit (SYSCON.10): 135 _ROMEN EQU 0 ; 0 = Internal ROM disabled 136 ; 1 = Internal ROM enabled 137 ; 138 ; SGTDIS: Segmentation Disable control bit (SYSCON.11): $IF TINY _SGTDIS EQU 1 ; disable segmented mode for TINY model 141 $ELSE 142 _SGTDIS EQU 0 ; enable segmented mode (Reset Value) 143 $ENDIF 144 ; 145 ; ROMS1: ROM Segment Mapping Control Bit (SYSCON.12): 146 _ROMS1 EQU 0 ; _ROMS1 = 0 Internal ROM mapped to segment 0 147 ; ; _ROMS1 = 1 Internal ROM mapped to segment 1 148 ; 149 ; STKSZ: Maximum System Stack Size selection (SYSCON.13 .. SYSCON.15) 150 ; Defines the system stack space which is used by CALL/RET and PUSH/POP 151 ; instructions. The system stack space must be adjusted according the 152 ; actual requirements of the application. 153 $SET (STK_SIZE = 0) 154 ; System stack sizes: 155 ; 0 = 256 words (Reset Value) 156 ; 1 = 128 words 157 ; 2 = 64 words 158 ; 3 = 32 words 159 ; 4 = 512 words 160 ; 5 = not implemented 161 ; 6 = not implemented 162 ; 7 = no wrapping (entire internal RAM use as STACK, set size with SYSSZ) 163 ; If you have selected 7 for STK_SIZE, you can set the actual system stack size 164 ; with the following SSTSZ statement. 165 SSTSZ EQU 200H ; set System Stack Size to 200H Bytes 166 ; 167 ; USTSZ: User Stack Size Definition 168 ; Defines the user stack space available for automatics. This stack space is 169 ; accessed by R0. The user stack space must be adjusted according the actual 170 ; requirements of the application. 171 USTSZ EQU 1000H ; set User Stack Size to 1000H Bytes. 172 ; 173 ; WATCHDOG: Disable Hardware Watchdog 174 ; --- Set WATCHDOG = 1 to enable the Hardware watchdog 175 $SET (WATCHDOG = 0) 176 ; 177 ; 178 ; CLR_MEMORY: Disable Memory Zero Initialization of RAM area 179 ; --- Set CLR_MEMORY = 0 to disable memory zero initilization 180 $SET (CLR_MEMORY = 1) 181 ; 182 ; INIT_VARS: Disable Variable Initialization 183 ; --- Set INIT_VARS = 0 to disable variable initilization 184 $SET (INIT_VARS = 1) 185 ; 186 ; DPPUSE: Re-assign DPP registers 187 ; --- Set DPPUSE = 0 to reduce the code size of the startup code, if you 188 ; are not using the L166 DPPUSE directive. 189 $SET (DPPUSE = 0) 190 ; 191 ; DPP3USE: Use DPP3 register during variable initilization A166 MACRO ASSEMBLER START 08/28/03 20:15:47 PAGE 4 192 ; --- Set DPP3USE = 0 to disable the usage of DPP3 during initilization of 193 ; variables. This option might be required if you write 194 ; program parts that are reloaded during application 195 ; execution and increase code size of the startup code. 196 $SET (DPP3USE = 1) 197 ; 198 ;------------------------------------------------------------------------------ 199 ; Initialization for XPERCON register (available on some derivatives only 200 ; 201 ; INIT_XPERCON: Init XPERCON register available on some devices 202 ; --- Set INIT_XPERCON = 1 to initilize the XPERCON register 203 $SET (INIT_XPERCON = 0) 204 ; 205 ; --- XPERCON values 206 ; 207 ; V_CAN1: make CAN1 address range 0xEF00 .. 0xEFFF visible (XPERCON.0) 208 V_CAN1 EQU 1 ; 0 = CAN1 is not visible on the XBUS 209 ; ; 1 = CAN1 is visible on the XBUS (default) 210 ; 211 ; V_CAN2: make CAN2 address range 0xEE00 .. 0xEEFF visible (XPERCON.1) 212 V_CAN2 EQU 0 ; 0 = CAN2 is not visible on the XBUS (default) 213 ; ; 1 = CAN2 is visible on the XBUS 214 ; 215 ; V_XRAM2: make 2KB XRAM address range 0xE000 .. 0xE7FF visible (XPERCON.10) 216 V_XRAM2 EQU 1 ; 0 = 2KB XRAM is not visible on the XBUS 217 ; ; 1 = 2KB XRAM is visible on the XBUS (default) 218 ; 219 ; V_XRAM6: make 6KB XRAM address range 0xC000 .. 0xD7FF visible (XPERCON.11) 220 V_XRAM6 EQU 0 ; 0 = 6KB XRAM is not visible on the XBUS (default) 221 ; ; 1 = 6KB XRAM is visible on the XBUS 222 ; 223 ; V_XFLASH: make 4KB XFLASH address range 0x8000 .. 0x8FFF visible (XPERCON.14) 224 V_XFLASH EQU 0 ; 0 = 4KB XFLASH is not visible on the XBUS (default) 225 ; ; 1 = 4KB XFLASH is visible on the XBUS 226 ; 227 ;------------------------------------------------------------------------------ 228 ; 229 ; Initialization for SYSCON2 and SYSCON3 (available on some derivatives only) 230 ; Note: The SYSCON2 and SYSCON3 bits may be different in some derivatives. 231 ; Check the values carefully! 232 ; 233 ; ADVANCED_SYSCON: Init SYSCON2 and SYSCON3 register available on some devices 234 ; --- Set ADVANCE_SYSCON = 1 to initilize SYSCON2 and SYSCON3 235 $SET (ADVANCED_SYSCON = 0) 236 ; 237 ; --- SYSCON2 values 238 ; 239 ; PDCON: Power Down Control (during power down mode) (SYSCON2.4 .. SYSCON2.5) 240 PDCON EQU 0 ; 0 = RTC On, Ports On (default after Reset) 241 ; ; 1 = RTC On, Ports Off 242 ; ; 2 = RTC Off, Ports On 243 ; ; 3 = RTC Off, Ports Off 244 ; 245 ; RTS: RTC Clock Source (not affected by a reset) (SYSCON2.6) 246 RTS EQU 0 ; 0 = Main oscillator 247 ; ; 1 = Auxiliary oscillator (if available) 248 ; 249 ; SCS: SDD Clock Source (not affected by a reset) (SYSCON2.7) 250 SCS EQU 0 ; 0 = Main oscillator 251 ; ; 1 = Auxiliary oscillator (if available) 252 ; 253 ; CLKCON: Clock State Control (SYSCON2.8 .. SYSCON2.9) 254 CLKCON EQU 0 ; 0 = Running on configured basic frequency 255 ; ; 1 = Running on slow down frequency, PLL ON 256 ; ; 2 = Running on slow down frequency, PLL OFF 257 ; ; 3 = reserved A166 MACRO ASSEMBLER START 08/28/03 20:15:47 PAGE 5 258 ; 259 ; CLKREL: Reload Counter Value for Slowdown Devider (SYSCON2.10 .. SYSCON2.14) 260 CLKREL EQU 0 ; possible values are 0 .. 31 261 ; 262 ; 263 ; --- SYSCON3 values: disable on-chip peripherals 264 ; 265 ADCDIS EQU 0 ; 1 = disable Analog/Digital Converter (SYSCON3.0) 266 ASC0DIS EQU 0 ; 1 = disable UART ASC0 (SYSCON3.1) 267 SSCDIS EQU 0 ; 1 = disable Synchronus Serial Cnl SSC (SYSCON3.2) 268 GPTDIS EQU 0 ; 1 = disable Timer Block GPT (SYSCON3.3) 269 ; reserved (SYSCON3.4) 270 FMDIS EQU 0 ; 1 = disable on-chip Flash Memory Module (SYSCON3.5) 271 CC1DIS EQU 0 ; 1 = disable CAPCOM Unit 1 (SYSCON3.6) 272 CC2DIS EQU 0 ; 1 = disable CAPCOM Unit 2 (SYSCON3.7) 273 CC6DIS EQU 0 ; 1 = disable CAPCOM Unit 6 (SYSCON3.8) 274 PWMDIS EQU 0 ; 1 = disable Pulse Width Modulation Unit (SYSCON3.9) 275 ASC1DIS EQU 0 ; 1 = disable UART ASC1 (SYSCON3.10) 276 I2CDIS EQU 0 ; 1 = disable I2C Bus Module (SYSCON3.11) 277 ; ; reserved (SYSCON3.12) 278 CAN1DIS EQU 0 ; 1 = disable on-chip CAN Module 1 (SYSCON3.13) 279 CAN2DIS EQU 0 ; 1 = disable on-chip CAN Module 2 (SYSCON3.14) 280 PCDDIS EQU 0 ; 1 = disable Peripheral Clock Driver (SYSCON3.15) 281 ; 282 ;------------------------------------------------------------------------------ 283 ; 284 ; BUSCON1/ADDRSEL1 .. BUSCON4/ADDRSEL4 Initialization 285 ; =================================================== 286 ; 287 ; 288 ; BUSCON1/ADDRSEL1 289 ; --- Set BUSCON1 = 1 to initialize the BUSCON1/ADDRSEL1 registers 290 $SET (BUSCON1 = 1) 291 ; 292 ; Define the start address and the address range of Chip Select 1 (CS1#) 293 ; This values are used to set the ADDRSEL1 register 294 ; Set CS1# Start Address (default 100000H) 295 ; Set CS1# Range (default 1024K = 1MB) 296 ; 297 ; MCTC1: Memory Cycle Time (BUSCON1.0 .. BUSCON1.3): 298 ; Note: if RDYEN1 == 1 a maximum number of 7 waitstates can be selected 299 _MCTC1 EQU 2 ; Memory wait states is 1 (MCTC1 field = 0EH). 300 ; 301 ; RWDC1: Read/Write Signal Delay (BUSCON1.4): 302 _RWDC1 EQU 1 ; 0 = Delay Time 0.5 States 303 ; ; 1 = No Delay Time 0 States 304 ; 305 ; MTTC1: Memory Tri-state Time (BUSCON1.5): 306 _MTTC1 EQU 0 ; 0 = Delay Time 0.5 States 307 ; ; 1 = No Delay Time 0 States 308 ; 309 ; BTYP1: External Bus Configuration Control (BUSCON1.6 .. BUSCON1.7): 310 _BTYP1 EQU 2 ; 0 = 8 Bit Non Multiplexed 311 ; ; 1 = 8 Bit Multiplexed 312 ; ; 2 = 16 Bit Non Multiplexed 313 ; ; 3 = 16 Bit Multiplexed 314 ; 315 ; ALECTL1: ALE Lengthening Control Bit (BUSCON1.9): 316 _ALECTL1 EQU 0 ; see data sheet for description 317 ; 318 ; BUSACT1: Bus Active Control Bit (BUSCON1.10): 319 _BUSACT1 EQU 1 ; = 0 external (ADDRSEL1) bus disabled 320 ; = 1 external (ADDRSEL1) bus enabled 321 ; 322 ; RDYEN1: READY# Input Enable control bit (BUSCON1.12): 323 _RDYEN1 EQU 0 ; 0 = READY# function disabled A166 MACRO ASSEMBLER START 08/28/03 20:15:47 PAGE 6 324 ; ; 1 = READY# function enabled 325 ; 326 ; RDY_AS1: Synchronous / Asynchronous READY# Input (BUSCON1.3): 327 ; Note: This bit is only valid if _RDYEN1 == 1. 328 _RDY_AS1 EQU 0 ; 0 = synchronous READY# input 329 ; ; 1 = asynchronous READY# input 330 ; 331 ; CSREN1: Read Chip Select Enable bit (BUSCON1.14): 332 _CSREN1 EQU 0 ; 0 = CS1# is independent of read command (RD#) 333 ; ; 1 = CS1# is generated for the duration of read 334 ; 335 ; CSWEN1: Write Chip Select Enable bit (BUSCON1.15): 336 _CSWEN1 EQU 0 ; 0 = CS1# is independent of write command (WR#) 337 ; ; 1 = CS1# is generated for the duration of write 338 ; 339 ; 340 ; BUSCON2/ADDRSEL2 341 ; --- Set BUSCON2 = 1 to initialize the BUSCON2/ADDRSEL2 registers 342 $SET (BUSCON2 = 0) 343 ; 344 ; Define the start address and the address range of Chip Select 2 (CS2#) 345 ; This values are used to set the ADDRSEL2 register 346 ; Set CS2# Start Address (default 200000H) 347 ; Set CS2# Range (default 1024K = 1MB) 348 ; 349 ; MCTC2: Memory Cycle Time (BUSCON2.0 .. BUSCON2.3): 350 ; Note: if RDYEN2 == 1 a maximum number of 7 waitstates can be selected 351 _MCTC2 EQU 2 ; Memory wait states is 1 (MCTC2 field = 0EH). 352 ; 353 ; RWDC2: Read/Write Signal Delay (BUSCON2.4): 354 _RWDC2 EQU 1 ; 0 = Delay Time 0.5 States 355 ; ; 1 = No Delay Time 0 States 356 ; 357 ; MTTC2: Memory Tri-state Time (BUSCON2.5): 358 _MTTC2 EQU 0 ; 0 = Delay Time 0.5 States 359 ; ; 1 = No Delay Time 0 States 360 ; 361 ; BTYP2: External Bus Configuration Control (BUSCON2.6 .. BUSCON2.7): 362 _BTYP2 EQU 2 ; 0 = 8 Bit Non Multiplexed 363 ; ; 1 = 8 Bit Multiplexed 364 ; ; 2 = 16 Bit Non Multiplexed 365 ; ; 3 = 16 Bit Multiplexed 366 ; 367 ; ALECTL2: ALE Lengthening Control Bit (BUSCON2.9): 368 _ALECTL2 EQU 0 ; see data sheet for description 369 ; 370 ; BUSACT2: Bus Active Control Bit (BUSCON2.10): 371 _BUSACT2 EQU 1 ; = 0 external (ADDRSEL2) bus disabled 372 ; = 1 external (ADDRSEL2) bus enabled 373 ; 374 ; RDYEN2: READY# Input Enable control bit (BUSCON2.12): 375 _RDYEN2 EQU 0 ; 0 = READY# function disabled 376 ; ; 1 = READY# function enabled 377 ; 378 ; RDY_AS2: Synchronous / Asynchronous READY# Input (BUSCON2.3): 379 ; Note: This bit is only valid if _RDYEN2 == 1. 380 _RDY_AS2 EQU 0 ; 0 = synchronous READY# input 381 ; ; 1 = asynchronous READY# input 382 ; 383 ; CSREN2: Read Chip Select Enable bit (BUSCON2.14): 384 _CSREN2 EQU 0 ; 0 = CS2# is independent of read command (RD#) 385 ; ; 1 = CS2# is generated for the duration of read 386 ; 387 ; CSWEN2: Write Chip Select Enable bit (BUSCON2.15): 388 _CSWEN2 EQU 0 ; 0 = CS2# is independent of write command (WR#) 389 ; ; 1 = CS2# is generated for the duration of write A166 MACRO ASSEMBLER START 08/28/03 20:15:47 PAGE 7 390 ; 391 ; 392 ; BUSCON3/ADDRSEL3 393 ; --- Set BUSCON3 = 1 to initialize the BUSCON3/ADDRSEL3 registers 394 $SET (BUSCON3 = 0) 395 ; 396 ; Define the start address and the address range of Chip Select 3 (CS3#) 397 ; This values are used to set the ADDRSEL3 register 398 ; Set CS3# Start Address (default 300000H) 399 ; Set CS3# Range (default 1024K = 1MB) 400 ; 401 ; MCTC3: Memory Cycle Time (BUSCON3.0 .. BUSCON3.3): 402 ; Note: if RDYEN3 == 1 a maximum number of 7 waitstates can be selected 403 _MCTC3 EQU 2 ; Memory wait states is 1 (MCTC3 field = 0EH). 404 ; 405 ; RWDC3: Read/Write Signal Delay (BUSCON3.4): 406 _RWDC3 EQU 1 ; 0 = Delay Time 0.5 States 407 ; ; 1 = No Delay Time 0 States 408 ; 409 ; MTTC3: Memory Tri-state Time (BUSCON3.5): 410 _MTTC3 EQU 0 ; 0 = Delay Time 0.5 States 411 ; ; 1 = No Delay Time 0 States 412 ; 413 ; BTYP3: External Bus Configuration Control (BUSCON3.6 .. BUSCON3.7): 414 _BTYP3 EQU 2 ; 0 = 8 Bit Non Multiplexed 415 ; ; 1 = 8 Bit Multiplexed 416 ; ; 2 = 16 Bit Non Multiplexed 417 ; ; 3 = 16 Bit Multiplexed 418 ; 419 ; ALECTL3: ALE Lengthening Control Bit (BUSCON3.9): 420 _ALECTL3 EQU 0 ; see data sheet for description 421 ; 422 ; BUSACT3: Bus Active Control Bit (BUSCON3.10): 423 _BUSACT3 EQU 1 ; = 0 external (ADDRSEL3) bus disabled 424 ; = 1 external (ADDRSEL3) bus enabled 425 ; 426 ; RDYEN3: READY# Input Enable control bit (BUSCON3.12): 427 _RDYEN3 EQU 0 ; 0 = READY# function disabled 428 ; ; 1 = READY# function enabled 429 ; 430 ; RDY_AS3: Synchronous / Asynchronous READY# Input (BUSCON3.3): 431 ; Note: This bit is only valid if _RDYEN3 == 1. 432 _RDY_AS3 EQU 0 ; 0 = synchronous READY# input 433 ; ; 1 = asynchronous READY# input 434 ; 435 ; CSREN3: Read Chip Select Enable bit (BUSCON3.14): 436 _CSREN3 EQU 0 ; 0 = CS3# is independent of read command (RD#) 437 ; ; 1 = CS3# is generated for the duration of read 438 ; 439 ; CSWEN3: Write Chip Select Enable bit (BUSCON3.15): 440 _CSWEN3 EQU 0 ; 0 = CS3# is independent of write command (WR#) 441 ; ; 1 = CS3# is generated for the duration of write 442 ; 443 ; 444 ; BUSCON4/ADDRSEL4 445 ; --- Set BUSCON4 = 1 to initialize the BUSCON4/ADDRSEL4 registers 446 $SET (BUSCON4 = 0) 447 ; 448 ; Define the start address and the address range of Chip Select 4 (CS4#) 449 ; This values are used to set the ADDRSEL4 register 450 ; Set CS4# Start Address (default 400000H) 451 ; Set CS4# Range (default 1024K = 1MB) 452 ; 453 ; MCTC4: Memory Cycle Time (BUSCON4.0 .. BUSCON4.3): 454 ; Note: if RDYEN4 == 1 a maximum number of 7 waitstates can be selected 455 _MCTC4 EQU 2 ; Memory wait states is 1 (MCTC4 field = 0EH). A166 MACRO ASSEMBLER START 08/28/03 20:15:47 PAGE 8 456 ; 457 ; RWDC4: Read/Write Signal Delay (BUSCON4.4): 458 _RWDC4 EQU 1 ; 0 = Delay Time 0.5 States 459 ; ; 1 = No Delay Time 0 States 460 ; 461 ; MTTC4: Memory Tri-state Time (BUSCON4.5): 462 _MTTC4 EQU 0 ; 0 = Delay Time 0.5 States 463 ; ; 1 = No Delay Time 0 States 464 ; 465 ; BTYP4: External Bus Configuration Control (BUSCON4.6 .. BUSCON4.7): 466 _BTYP4 EQU 2 ; 0 = 8 Bit Non Multiplexed 467 ; ; 1 = 8 Bit Multiplexed 468 ; ; 2 = 16 Bit Non Multiplexed 469 ; ; 3 = 16 Bit Multiplexed 470 ; 471 ; ALECTL4: ALE Lengthening Control Bit (BUSCON4.9): 472 _ALECTL4 EQU 0 ; see data sheet for description 473 ; 474 ; BUSACT4: Bus Active Control Bit (BUSCON4.10): 475 _BUSACT4 EQU 1 ; = 0 external (ADDRSEL4) bus disabled 476 ; = 1 external (ADDRSEL4) bus enabled 477 ; 478 ; RDYEN4: READY# Input Enable control bit (BUSCON4.12): 479 _RDYEN4 EQU 0 ; 0 = READY# function disabled 480 ; ; 1 = READY# function enabled 481 ; 482 ; RDY_AS4: Synchronous / Asynchronous READY# Input (BUSCON4.3): 483 ; Note: This bit is only valid if _RDYEN4 == 1. 484 _RDY_AS4 EQU 0 ; 0 = synchronous READY# input 485 ; ; 1 = asynchronous READY# input 486 ; 487 ; CSREN4: Read Chip Select Enable bit (BUSCON4.14): 488 _CSREN4 EQU 0 ; 0 = CS4# is independent of read command (RD#) 489 ; ; 1 = CS4# is generated for the duration of read 490 ; 491 ; CSWEN4: Write Chip Select Enable bit (BUSCON4.15): 492 _CSWEN4 EQU 0 ; 0 = CS4# is independent of write command (WR#) 493 ; ; 1 = CS4# is generated for the duration of write 494 ; 495 ;------------------------------------------------------------------------------ 496 $IF TINY $SET (DPPUSE = 0) 499 $ENDIF 500 501 _STKSZ SET 0 502 _STKSZ1 SET 0 ; size is 512 Words 503 $IF (STK_SIZE = 0) 504 _STKSZ1 SET 1 ; size is 256 Words 505 $ENDIF $IF (STK_SIZE = 1) _STKSZ SET 1 _STKSZ1 SET 2 ; size is 128 Words 509 $ENDIF $IF (STK_SIZE = 2) _STKSZ SET 2 _STKSZ1 SET 3 ; size is 64 Words 513 $ENDIF $IF (STK_SIZE = 3) _STKSZ SET 3 _STKSZ1 SET 4 ; size is 32 Words 517 $ENDIF $IF (STK_SIZE = 4) _STKSZ SET 4 520 $ENDIF $IF (STK_SIZE = 5) A166 MACRO ASSEMBLER START 08/28/03 20:15:47 PAGE 9 _STKSZ SET 5 523 $ENDIF $IF (STK_SIZE = 6) _STKSZ SET 6 526 $ENDIF $IF (STK_SIZE = 7) _STKSZ SET 7 529 $ENDIF 530 531 532 $IF NOT TINY 533 ASSUME DPP3:SYSTEM 534 ASSUME DPP2:NDATA 535 $ENDIF 536 537 NAME ?C_STARTUP 538 PUBLIC ?C_STARTUP 539 540 $IF MEDIUM OR LARGE OR HLARGE 541 Model LIT 'FAR' $ELSE Model LIT 'NEAR' 544 $ENDIF 545 546 EXTRN main:FAR 547 548 PUBLIC ?C_USRSTKBOT 549 550 ?C_USERSTACK SECTION DATA PUBLIC 'NDATA' 551 $IF NOT TINY 552 NDATA DGROUP ?C_USERSTACK 553 $ENDIF 554 ?C_USRSTKBOT: 000000 555 DS USTSZ ; Size of User Stack 556 ?C_USERSTKTOP: 557 ?C_USERSTACK ENDS 558 559 ?C_MAINREGISTERS REGDEF R0 - R15 560 $IF (STK_SIZE = 7) ?C_SYSSTACK SECTION DATA PUBLIC 'IDATA' $IF NOT TINY SDATA DGROUP ?C_SYSSTACK $ENDIF _BOS: ; bottom of system stack DS SSTSZ ; Size of User Stack _TOS: ; top of system stack ?C_SYSSTACK ENDS 572 $ELSE 573 ; Setup Stack Overflow 574 _TOS EQU 0FC00H ; top of system stack 575 _BOS EQU _TOS - (1024 >> _STKSZ1) ; bottom of system stack 576 $ENDIF 577 578 PUBLIC ?C_SYSSTKBOT 579 ?C_SYSSTKBOT EQU _BOS 580 581 SSKDEF _STKSZ ; System stack size 582 583 ?C_STARTUP_CODE SECTION CODE 'ICODE' 584 585 586 ;------------------------------------------------------------------------------ 587 A166 MACRO ASSEMBLER START 08/28/03 20:15:47 PAGE 10 588 ; Special Function Register Addresses 589 SYSCON DEFR 0FF12H 590 BUSCON0 DEFR 0FF0CH 591 SP DEFR 0FE12H 592 STKOV DEFR 0FE14H 593 STKUN DEFR 0FE16H 594 P3 DEFR 0FFC4H 595 DP3 DEFR 0FFC6H 596 BUSCON1 DEFR 0FF14H 597 BUSCON2 DEFR 0FF16H 598 BUSCON3 DEFR 0FF18H 599 BUSCON4 DEFR 0FF1AH 600 ADDRSEL1 DEFR 0FE18H 601 ADDRSEL2 DEFR 0FE1AH 602 ADDRSEL3 DEFR 0FE1CH 603 ADDRSEL4 DEFR 0FE1EH 604 SYSCON2 DEFR 0F1D0H 605 SYSCON3 DEFR 0F1D4H 606 607 608 609 610 ; --------------------------------------------------------------------- 611 ; Uncomment one of the following lines: 612 ?C_RESET PROC TASK C_STARTUP INTNO RESET = 0 613 ; THE ABOVE LINE CREATES A RESET VECTOR AT 0000H TO 614 ; START PROGRAM EXECUTION (f.e. Software in Flash)!! 615 ; C_RESET PROC NEAR 616 ; THE ABOVE LINE DOES NOT CREATE ANY RESET VECTOR!! 617 ; PROGRAM EXECUTION HAS TO BE STARTED BY ANY MANUAL JUMP 618 ; (f.e. by bootstrap loader, GO command within monitor)!! 619 ; --------------------------------------------------------------------- 620 621 ?C_STARTUP: LABEL FAR 622 623 624 $IF (WATCHDOG = 0) 000000 A55AA5A5 625 DISWDT ; Disable watchdog timer 626 $ENDIF 627 $IF (INIT_XPERCON = 1) ; Improtant XPERCON must be set before SYSCON.XPEN is enabled XPERCON DEFR 0F024H V_XPERCON SET V_CAN1 OR (V_CAN2 << 1) OR (V_XRAM2 << 10) V_XPERCON SET V_XPERCON OR (V_XRAM6 << 11) OR (V_XFLASH << 14) EXTR #1 MOV XPERCON,#V_XPERCON 635 $ENDIF 636 637 BCON0L SET (_MTTC0 << 5) OR (_RWDC0 << 4) 638 BCON0L SET BCON0L OR ((NOT _MCTC0) AND 0FH) 639 BCON0L SET BCON0L AND (NOT (_RDYEN0 << 3)) 640 BCON0L SET BCON0L OR (_RDY_AS0 << 3) 641 BCON0H SET (_ALECTL0 << 1) OR (_RDYEN0 << 4) 642 BCON0H SET BCON0H OR (_CSREN0 << 6) OR (_CSWEN0 << 7) $IF (BTYP_ENABLE == 1) BCON0L SET BCON0L OR (_BTYP0 << 6) BCON0H SET BCON0H OR (_BUSACT0 << 2) 646 $ENDIF 647 648 $IF (BTYP_ENABLE == 0) 000004 0A863F1D 649 BFLDL BUSCON0,#03FH,#BCON0L 000008 1A8600D2 650 BFLDH BUSCON0,#0D2H,#BCON0H $ELSE BFLDL BUSCON0,#0FFH,#BCON0L BFLDH BUSCON0,#0D6H,#BCON0H A166 MACRO ASSEMBLER START 08/28/03 20:15:47 PAGE 11 654 $ENDIF 655 SYS_BITS SET 0FF6FH 656 657 SYS_H SET (_STKSZ << 5) OR (_ROMS1 << 4) OR (_SGTDIS << 3) 658 SYS_H SET SYS_H OR (_ROMEN << 2) OR (_BYTDIS << 1) OR _CLKEN 659 SYS_L SET _XPERSHARE OR (_VISIBLE << 1) OR (_XPEN << 2) 660 SYS_L SET SYS_L OR (_BDRSTEN << 3) 661 SYS_L SET SYS_L OR (_PWDCFG << 5) OR (_CSCFG << 6) $IF (WRCFG_ENABLE == 1) SYS_L SET SYS_L OR (_WRCFG << 7) SYS_BITS SET SYS_BITS OR 00080H 665 $ENDIF $IF (OWDDIS_ENABLE == 1) SYS_L SET SYS_L OR (_OWDDIS << 4) SYS_BITS SET SYS_BITS OR 00010H 669 $ENDIF 670 ; Setup SYSCON Register 671 00000C 1A8900FF 672 BFLDH SYSCON,#HIGH SYS_BITS,#SYS_H 000010 0A896F04 673 BFLDL SYSCON,#LOW SYS_BITS,#SYS_L 674 ; $IF (ADVANCED_SYSCON = 1) SYS_2 SET (PDCON << 4) OR (RTS << 6) OR (SCS << 7) SYS_2 SET SYS_2 OR (CLKCON << 8) OR (CLKREL << 10) SYS_3 SET ADCDIS OR (ASC0DIS << 1) OR (SSCDIS << 2) SYS_3 SET SYS_3 OR (GPTDIS << 3) SYS_3 SET SYS_3 OR (FMDIS << 5) OR (CC1DIS << 6) OR (CC2DIS << 7) SYS_3 SET SYS_3 OR (CC6DIS << 8) OR (PWMDIS << 9) SYS_3 SET SYS_3 OR (ASC1DIS << 10) OR (I2CDIS << 11) SYS_3 SET SYS_3 OR (CAN1DIS << 13) OR (CAN2DIS << 14) SYS_3 SET SYS_3 OR (PCDDIS << 15) EXTR #2 MOV SYSCON2,#SYS_2 MOV SYSCON3,#SYS_3 690 $ENDIF 691 ; 692 693 $IF (BUSCON1 = 1) 694 BCON1 SET (_MTTC1 << 5) OR (_RWDC1 << 4) 695 BCON1 SET BCON1 OR ((NOT _MCTC1) AND 0FH) 696 BCON1 SET BCON1 AND (NOT (_RDYEN1 << 3)) 697 BCON1 SET BCON1 OR (_RDY_AS1 << 3) OR (_BTYP1 << 6) 698 BCON1 SET BCON1 OR (_ALECTL1 << 9) OR (_BUSACT1 << 10) 699 BCON1 SET BCON1 OR (_RDYEN1 << 12) OR (_CSREN1 << 14) 700 BCON1 SET BCON1 OR (_CSWEN1 << 15) 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 A166 MACRO ASSEMBLER START 08/28/03 20:15:47 PAGE 12 720 ADDR1 EQU 1008H 721 000014 E60C0810 722 MOV ADDRSEL1,#ADDR1 000018 E68A9D04 723 MOV BUSCON1,#BCON1 724 $ENDIF 725 $IF (BUSCON2 = 1) BCON2 SET (_MTTC2 << 5) OR (_RWDC2 << 4) BCON2 SET BCON2 OR ((NOT _MCTC2) AND 0FH) BCON2 SET BCON2 AND (NOT (_RDYEN2 << 3)) BCON2 SET BCON2 OR (_RDY_AS2 << 3) OR (_BTYP2 << 6) BCON2 SET BCON2 OR (_ALECTL2 << 9) OR (_BUSACT2 << 10) BCON2 SET BCON2 OR (_RDYEN2 << 12) OR (_CSREN2 << 14) BCON2 SET BCON2 OR (_CSWEN2 << 15) ADDR2 EQU 2008H MOV ADDRSEL2,#ADDR2 MOV BUSCON2,#BCON2 757 $ENDIF 758 $IF (BUSCON3 = 1) BCON3 SET (_MTTC3 << 5) OR (_RWDC3 << 4) BCON3 SET BCON3 OR ((NOT _MCTC3) AND 0FH) BCON3 SET BCON3 AND (NOT (_RDYEN3 << 3)) BCON3 SET BCON3 OR (_RDY_AS3 << 3) OR (_BTYP3 << 6) BCON3 SET BCON3 OR (_ALECTL3 << 9) OR (_BUSACT3 << 10) BCON3 SET BCON3 OR (_RDYEN3 << 12) OR (_CSREN3 << 14) BCON3 SET BCON3 OR (_CSWEN3 << 15) A166 MACRO ASSEMBLER START 08/28/03 20:15:47 PAGE 13 ADDR3 EQU 3008H MOV ADDRSEL3,#ADDR3 MOV BUSCON3,#BCON3 790 $ENDIF 791 $IF (BUSCON4 = 1) BCON4 SET (_MTTC4 << 5) OR (_RWDC4 << 4) BCON4 SET BCON4 OR ((NOT _MCTC4) AND 0FH) BCON4 SET BCON4 AND (NOT (_RDYEN4 << 3)) BCON4 SET BCON4 OR (_RDY_AS4 << 3) OR (_BTYP4 << 6) BCON4 SET BCON4 OR (_ALECTL4 << 9) OR (_BUSACT4 << 10) BCON4 SET BCON4 OR (_RDYEN4 << 12) OR (_CSREN4 << 14) BCON4 SET BCON4 OR (_CSWEN4 << 15) ADDR4 EQU 4008H MOV ADDRSEL4,#ADDR4 MOV BUSCON4,#BCON4 823 $ENDIF 824 825 826 $IF (STK_SIZE = 7) MOV STKUN,#0FFFEH ; AVOID STKUN TRAP MOV STKOV,#0H ; AVOID STKOV TRAP MOV SP,#DPP3:_TOS ; INITIALIZE STACK POINTER MOV STKUN,#DPP3:_TOS ; INITIALIZE STACK UNFL REGISTER MOV STKOV,#DPP3:(_BOS+6*2) ; INITIALIZE STACK OVFL REGISTER 833 $ELSE 00001C E60A0CFA 834 MOV STKOV,#(_BOS+6*2) ; INITIALIZE STACK OVFL REGISTER 835 $ENDIF 836 837 $IF NOT TINY 838 839 EXTRN ?C_PAGEDPP0 : DATA16 840 EXTRN ?C_PAGEDPP1 : DATA16 841 EXTRN ?C_PAGEDPP2 : DATA16 842 $IF (DPPUSE = 1) MOV DPP0,#?C_PAGEDPP0 ; INIT DPP0 VALUE 845 $ENDIF 000020 E6010000 E 846 MOV DPP1,#?C_PAGEDPP1 ; DEFAULT NEAR CONST PAGE 000024 E6020000 E 847 MOV DPP2,#?C_PAGEDPP2 ; DEFAULT NEAR DATA PAGE 848 849 $ENDIF 850 000028 E6080000 R 851 MOV CP,#?C_MAINREGISTERS A166 MACRO ASSEMBLER START 08/28/03 20:15:47 PAGE 14 00002C B54AB5B5 852 EINIT 853 854 ;$IF NOT TINY 855 ; MOV R0,#DPP2:?C_USERSTKTOP 856 ;$ELSE 000030 E6F00010 R 857 MOV R0,#?C_USERSTKTOP 858 ;$ENDIF 859 860 861 ;------------------------------------------------------------------------------ 862 ; 863 ; The following code is necessary to set RAM variables to 0 at start-up 864 ; (RESET) of the C application program. 865 ; 866 867 $IF (CLR_MEMORY = 1) 868 869 EXTRN ?C_CLRMEMSECSTART : WORD 870 Clr_Memory: $IF TINY MOV R8,#?C_CLRMEMSECSTART JMPR cc_Z,EndClear RepeatClear: $IF (WATCHDOG = 1) SRVWDT ; SERVICE WATCHDOG $ENDIF MOV R5,#0 MOV R2,[R8+] ; Count JMPR cc_Z,EndClear MOV R3,R2 MOV R4,[R8+] JBC R2.14,ClearNear ClearBit: MOV R3,R4 SHR R3,#3 BCLR R3.0 ADD R3,#0FD00H ; START OF BIT SPACE MOV R5,#1 SHL R5,R4 CPL R5 AND R5,[R3] MOV [R3],R5 ADD R4,#1 SUB R2,#1 JMPR cc_NZ,ClearBit JMPR cc_UC,RepeatClear ClearNear: $IF (WATCHDOG = 1) SRVWDT ; SERVICE WATCHDOG $ENDIF MOVB [R4],RL5 ADD R4,#1 SUB R2,#1 JMPR cc_NN,ClearNear JMPR cc_UC,RepeatClear 910 $ELSE 000034 E6F90000 E 911 MOV R9,#SEG (?C_CLRMEMSECSTART) 000038 E6F80000 E 912 MOV R8,#SOF (?C_CLRMEMSECSTART) 00003C F018 913 MOV R1,R8 00003E 7019 914 OR R1,R9 000040 2D29 915 JMPR cc_Z,EndClear 916 917 RepeatClear: A166 MACRO ASSEMBLER START 08/28/03 20:15:47 PAGE 15 $IF (WATCHDOG = 1) SRVWDT ; SERVICE WATCHDOG 920 $ENDIF 000042 E005 921 MOV R5,#0 000044 DC09 922 EXTS R9,#1 000046 9828 923 MOV R2,[R8+] ; Count 000048 2D25 924 JMPR cc_Z,EndClear 00004A F032 925 MOV R3,R2 00004C DC09 926 EXTS R9,#1 00004E 9848 927 MOV R4,[R8+] 000050 AAF21BE0 928 JBC R2.14,ClearNear 000054 AAF20EF0 929 JBC R2.15,ClearFar 930 000058 F034 931 ClearBit: MOV R3,R4 00005A 7C33 932 SHR R3,#3 00005C 0EF3 933 BCLR R3.0 00005E 06F300FD 934 ADD R3,#0FD00H ; START OF BIT SPACE 000062 E015 935 MOV R5,#1 000064 4C54 936 SHL R5,R4 000066 9150 937 CPL R5 000068 685B 938 AND R5,[R3] 00006A B853 939 MOV [R3],R5 00006C 0841 940 ADD R4,#1 00006E 2821 941 SUB R2,#1 000070 3DF3 942 JMPR cc_NZ,ClearBit 000072 0DE7 943 JMPR cc_UC,RepeatClear 944 000074 DC09 945 ClearFar: EXTS R9,#1 000076 9838 946 MOV R3,[R8+] 947 RepClearFar: $IF (WATCHDOG = 1) SRVWDT ; SERVICE WATCHDOG 950 $ENDIF 000078 DC44 951 EXTP R4,#1 00007A B9A3 952 MOVB [R3],RL5 00007C 0831 953 ADD R3,#1 00007E 1840 954 ADDC R4,#0 000080 76F300C0 955 OR R3,#0C000H 000084 2821 956 SUB R2,#1 000086 7DF8 957 JMPR cc_NN,RepClearFar 000088 0DDC 958 JMPR cc_UC,RepeatClear 959 960 ClearNear: $IF (WATCHDOG = 1) SRVWDT ; SERVICE WATCHDOG 963 $ENDIF 00008A B9A4 964 MOVB [R4],RL5 00008C 0841 965 ADD R4,#1 00008E 2821 966 SUB R2,#1 000090 7DFC 967 JMPR cc_NN,ClearNear 000092 0DD7 968 JMPR cc_UC,RepeatClear 969 $ENDIF 970 971 EndClear: 972 973 $ENDIF 974 975 ;------------------------------------------------------------------------------ 976 ; 977 ; The following code is necessary, if the application program contains 978 ; initialized variables at file level. 979 ; 980 981 $IF (INIT_VARS = 1) ; ********************************************************* 982 983 EXTRN ?C_INITSECSTART : WORD A166 MACRO ASSEMBLER START 08/28/03 20:15:47 PAGE 16 984 Init_Vars: $IF TINY ; ******************************************************************** MOV R8,#?C_INITSECSTART RepeatInit: $IF (WATCHDOG = 1) SRVWDT ; SERVICE WATCHDOG $ENDIF MOV R2,[R8+] JMPR cc_Z,EndInit JBC R2.15,InitBit MOV R4,R2 AND R2,#3FFFH JMPR cc_NZ,LenLoad MOV R4,#0 MOV R2,[R8+] LenLoad: MOV R3,[R8+] CopyInitVal: MOVB [R3],[R8+] $IF (WATCHDOG = 1) SRVWDT ; SERVICE WATCHDOG $ENDIF ADD R3,#1 SUB R2,#1 JMPR cc_NZ,CopyInitVal JNB R8.0,RepeatInit ADD R8,#1 JMPR cc_UC,RepeatInit InitBit: MOVBZ R3,RL2 SHL R3,#1 OR R3,#0FD00H ; START OF BIT SPACE MOV R4,#1 MOVB RL5,RH2 SHL R4,R5 ; CALCULATE BIT MASK JB R2.7,SetBit CPL R4 ; CLEAR BIT AND R4,[R3] JMPR cc_UC,StoreBit SetBit: OR R4,[R3] ; SET BIT StoreBit: MOV [R3],R4 JMPR cc_UC,RepeatInit EndInit: 1027 $ELSE ; $IF TINY ************************************************************** 000094 E6F90000 E 1028 MOV R9,#SEG (?C_INITSECSTART) 000098 E6F80000 E 1029 MOV R8,#SOF (?C_INITSECSTART) 1030 $IF (DPP3USE = 1) ; *********************************************************** 1031 RepeatInit: $IF (WATCHDOG = 1) SRVWDT ; SERVICE WATCHDOG 1034 $ENDIF 00009C E6030300 1035 MOV DPP3,#3 0000A0 DC09 1036 EXTS R9,#1 0000A2 A828 1037 MOV R2,[R8] 0000A4 2D3C 1038 JMPR cc_Z,EndInit 0000A6 0882 1039 ADD R8,#2 0000A8 1890 1040 ADDC R9,#0 0000AA AAF229F0 1041 JBC R2.15,InitBit 0000AE F042 1042 MOV R4,R2 0000B0 66F2FF3F 1043 AND R2,#3FFFH 0000B4 3D05 1044 JMPR cc_NZ,LenLoad 0000B6 E004 1045 MOV R4,#0 0000B8 DC09 1046 EXTS R9,#1 0000BA A828 1047 MOV R2,[R8] 0000BC 0882 1048 ADD R8,#2 0000BE 1890 1049 ADDC R9,#0 A166 MACRO ASSEMBLER START 08/28/03 20:15:47 PAGE 17 0000C0 DC09 1050 LenLoad: EXTS R9,#1 0000C2 A838 1051 MOV R3,[R8] 0000C4 0882 1052 ADD R8,#2 0000C6 1890 1053 ADDC R9,#0 0000C8 8AF406E0 1054 JB R4.14,CopyInitVal 0000CC F6F306FE 1055 MOV DPP3,R3 0000D0 DC09 1056 EXTS R9,#1 0000D2 A838 1057 MOV R3,[R8] 0000D4 0882 1058 ADD R8,#2 0000D6 1890 1059 ADDC R9,#0 0000D8 DC09 1060 CopyInitVal: EXTS R9,#1 0000DA A9A8 1061 MOVB RL5,[R8] 0000DC 0881 1062 ADD R8,#1 0000DE 1890 1063 ADDC R9,#0 0000E0 B9A3 1064 MOVB [R3],RL5 0000E2 0831 1065 ADD R3,#1 0000E4 8AF406E0 1066 JB R4.14,NoDPP3Adj 0000E8 8AF304E0 1067 JB R3.14,NoDPP3Adj 0000EC 06030100 1068 ADD DPP3,#1 0000F0 76F300C0 1069 OR R3,#0C000H ; SET DPP3 Bits 1070 NoDPP3Adj: $IF (WATCHDOG = 1) SRVWDT ; SERVICE WATCHDOG 1073 $ENDIF 0000F4 2821 1074 SUB R2,#1 0000F6 3DF0 1075 JMPR cc_NZ,CopyInitVal 0000F8 9AF8D000 1076 JNB R8.0,RepeatInit 0000FC 0881 1077 ADD R8,#1 0000FE 0DCE 1078 JMPR cc_UC,RepeatInit 1079 000100 C043 1080 InitBit: MOVBZ R3,RL2 000102 5C13 1081 SHL R3,#1 000104 76F300FD 1082 OR R3,#0FD00H ; START OF BIT SPACE 000108 E014 1083 MOV R4,#1 00010A F1A5 1084 MOVB RL5,RH2 00010C 4C45 1085 SHL R4,R5 ; CALCULATE BIT MASK 00010E 8AF20370 1086 JB R2.7,SetBit 000112 9140 1087 CPL R4 ; CLEAR BIT 000114 684B 1088 AND R4,[R3] 000116 0D01 1089 JMPR cc_UC,StoreBit 000118 784B 1090 SetBit: OR R4,[R3] ; SET BIT 00011A B843 1091 StoreBit: MOV [R3],R4 00011C 0DBF 1092 JMPR cc_UC,RepeatInit 1093 $ELSE ; block IF (DPP3USE = 1) ************************************************ RepeatInit: $IF (WATCHDOG = 1) SRVWDT ; SERVICE WATCHDOG $ENDIF EXTS R9,#1 MOV R2,[R8] JMPR cc_Z,EndInit ADD R8,#2 ADDC R9,#0 JBC R2.15,InitBit MOV R4,R2 AND R2,#3FFFH JMPR cc_NZ,LenLoad MOV R4,#0 EXTS R9,#1 MOV R2,[R8] ADD R8,#2 ADDC R9,#0 LenLoad: EXTS R9,#1 MOV R3,[R8] ADD R8,#2 A166 MACRO ASSEMBLER START 08/28/03 20:15:47 PAGE 18 ADDC R9,#0 JB R4.14,CopyNearVal MOV R6,R3 EXTS R9,#1 MOV R3,[R8] ADD R8,#2 ADDC R9,#0 CopyInitVal: OR R6,#0C000H EXTP R6,#1 MOV [R3],RL5 ADD R3,#1 ADDC R6,#0 $IF (WATCHDOG = 1) SRVWDT ; SERVICE WATCHDOG $ENDIF SUB R2,#1 JMPR cc_NZ,CopyInitVal JMPR cc_UC,CopyInitDone CopyNearVal: EXTS R9,#1 MOVB RL5,[R8] ADD R8,#1 ADDC R9,#0 MOVB [R3],RL5 ADD R3,#1 $IF (WATCHDOG = 1) SRVWDT ; SERVICE WATCHDOG $ENDIF SUB R2,#1 JMPR cc_NZ,CopyNearVal CopyInitDone: JNB R8.0,RepeatInit ADD R8,#1 JMPR cc_UC,RepeatInit InitBit: MOVBZ R3,RL2 SHL R3,#1 OR R3,#0FD00H ; START OF BIT SPACE MOV R4,#1 MOVB RL5,RH2 SHL R4,R5 ; CALCULATE BIT MASK JB R2.7,SetBit CPL R4 ; CLEAR BIT AND R4,[R3] JMPR cc_UC,StoreBit SetBit: OR R4,[R3] ; SET BIT StoreBit: MOV [R3],R4 JMPR cc_UC,RepeatInit 1164 $ENDIF ; close block IF (DPP3USE = 1) **************************************** 1165 1166 EndInit: 1167 1168 $ENDIF ; close block $IF TINY ************************************************ 1169 1170 $ENDIF ; close $IF (INIT_VARS = 1) ******************************************* 1171 1172 ;------------------------------------------------------------------------------ 1173 $IF TINY JMP main 1176 $ELSE 00011E FA000000 E 1177 JMP FAR main 1178 $ENDIF 1179 1180 ?C_RESET ENDP 1181 ?C_STARTUP_CODE ENDS A166 MACRO ASSEMBLER START 08/28/03 20:15:47 PAGE 19 1182 1183 $IF (INIT_VARS = 1) 1184 EXTERN ?C_ENDINIT:WORD 1185 $ENDIF 1186 1187 END A166 MACRO ASSEMBLER START 08/28/03 20:15:47 PAGE 20 SYMBOL TABLE LISTING ------ ----- ------- N A M E TYPE VALUE I ATTRIBUTES ?C_CLRMEMSECSTART. WORD ---- EXT ?C_ENDINIT . . . . WORD ---- EXT ?C_INITSECSTART. . WORD ---- EXT ?C_MAINREGISTERS . ---- ---- REGBANK ?C_PAGEDPP0. . . . DAT16 ---- EXT ?C_PAGEDPP1. . . . DAT16 ---- EXT ?C_PAGEDPP2. . . . DAT16 ---- EXT ?C_RESET . . . . . FAR 0H R SEC=?C_STARTUP_CODE ?C_STARTUP . . . . FAR 0H R PUB SEC=?C_STARTUP_CODE ?C_STARTUP_CODE. . ---- ---- SECTION ?C_SYSSTKBOT . . . DAT16 FA00H A PUB ?C_USERSTACK . . . ---- ---- SECTION ?C_USERSTKTOP. . . BYTE 1000H R SEC=?C_USERSTACK ?C_USRSTKBOT . . . BYTE 0H R PUB SEC=?C_USERSTACK ADCDIS . . . . . . DATA3 0H A ADDR1. . . . . . . DAT16 1008H A ADDRSEL1 . . . . . WORD FE18H A SFR ADDRSEL2 . . . . . WORD FE1AH A SFR ADDRSEL3 . . . . . WORD FE1CH A SFR ADDRSEL4 . . . . . WORD FE1EH A SFR ASC0DIS. . . . . . DATA3 0H A ASC1DIS. . . . . . DATA3 0H A BCON0H . . . . . . DATA3 0H A BCON0L . . . . . . DATA8 1DH A BCON1. . . . . . . DAT16 49DH A BUSCON0. . . . . . WORD FF0CH A SFR BUSCON1. . . . . . WORD FF14H A SFR BUSCON2. . . . . . WORD FF16H A SFR BUSCON3. . . . . . WORD FF18H A SFR BUSCON4. . . . . . WORD FF1AH A SFR CAN1DIS. . . . . . DATA3 0H A CAN2DIS. . . . . . DATA3 0H A CC1DIS . . . . . . DATA3 0H A CC2DIS . . . . . . DATA3 0H A CC6DIS . . . . . . DATA3 0H A CLKCON . . . . . . DATA3 0H A CLKREL . . . . . . DATA3 0H A CP . . . . . . . . WORD FE10H A SFR C_STARTUP. . . . . ---- ---- ClearBit . . . . . NEAR 58H R SEC=?C_STARTUP_CODE ClearFar . . . . . NEAR 74H R SEC=?C_STARTUP_CODE ClearNear. . . . . NEAR 8AH R SEC=?C_STARTUP_CODE Clr_Memory . . . . NEAR 34H R SEC=?C_STARTUP_CODE CopyInitVal. . . . NEAR D8H R SEC=?C_STARTUP_CODE DP3. . . . . . . . WORD FFC6H A SFR DPP1 . . . . . . . WORD FE02H A SFR DPP2 . . . . . . . WORD FE04H A SFR DPP3 . . . . . . . WORD FE06H A SFR EndClear . . . . . NEAR 94H R SEC=?C_STARTUP_CODE EndInit. . . . . . NEAR 11EH R SEC=?C_STARTUP_CODE FMDIS. . . . . . . DATA3 0H A GPTDIS . . . . . . DATA3 0H A I2CDIS . . . . . . DATA3 0H A InitBit. . . . . . NEAR 100H R SEC=?C_STARTUP_CODE Init_Vars. . . . . NEAR 94H R SEC=?C_STARTUP_CODE LenLoad. . . . . . NEAR C0H R SEC=?C_STARTUP_CODE Model. . . . . . . LIT "FAR" NDATA. . . . . . . ---- ---- GROUP NoDPP3Adj. . . . . NEAR F4H R SEC=?C_STARTUP_CODE P3 . . . . . . . . WORD FFC4H A SFR A166 MACRO ASSEMBLER START 08/28/03 20:15:47 PAGE 21 PCDDIS . . . . . . DATA3 0H A PDCON. . . . . . . DATA3 0H A PWMDIS . . . . . . DATA3 0H A RESET. . . . . . . INTNO 0000H RTS. . . . . . . . DATA3 0H A RepClearFar. . . . NEAR 78H R SEC=?C_STARTUP_CODE RepeatClear. . . . NEAR 42H R SEC=?C_STARTUP_CODE RepeatInit . . . . NEAR 9CH R SEC=?C_STARTUP_CODE SCS. . . . . . . . DATA3 0H A SP . . . . . . . . WORD FE12H A SFR SSCDIS . . . . . . DATA3 0H A SSTSZ. . . . . . . DAT16 200H A STKOV. . . . . . . WORD FE14H A SFR STKUN. . . . . . . WORD FE16H A SFR SYSCON . . . . . . WORD FF12H A SFR SYSCON2. . . . . . WORD F1D0H A ESF SYSCON3. . . . . . WORD F1D4H A ESF SYS_BITS . . . . . DAT16 FF6FH A SYS_H. . . . . . . DATA3 0H A SYS_L. . . . . . . DATA3 4H A SetBit . . . . . . NEAR 118H R SEC=?C_STARTUP_CODE StoreBit . . . . . NEAR 11AH R SEC=?C_STARTUP_CODE USTSZ. . . . . . . DAT16 1000H A V_CAN1 . . . . . . DATA3 1H A V_CAN2 . . . . . . DATA3 0H A V_XFLASH . . . . . DATA3 0H A V_XRAM2. . . . . . DATA3 1H A V_XRAM6. . . . . . DATA3 0H A _ALECTL0 . . . . . DATA3 0H A _ALECTL1 . . . . . DATA3 0H A _ALECTL2 . . . . . DATA3 0H A _ALECTL3 . . . . . DATA3 0H A _ALECTL4 . . . . . DATA3 0H A _BDRSTEN . . . . . DATA3 0H A _BOS . . . . . . . DAT16 FA00H A _BTYP0 . . . . . . DATA3 2H A _BTYP1 . . . . . . DATA3 2H A _BTYP2 . . . . . . DATA3 2H A _BTYP3 . . . . . . DATA3 2H A _BTYP4 . . . . . . DATA3 2H A _BUSACT0 . . . . . DATA3 1H A _BUSACT1 . . . . . DATA3 1H A _BUSACT2 . . . . . DATA3 1H A _BUSACT3 . . . . . DATA3 1H A _BUSACT4 . . . . . DATA3 1H A _BYTDIS. . . . . . DATA3 0H A _CLKEN . . . . . . DATA3 0H A _CSCFG . . . . . . DATA3 0H A _CSREN0. . . . . . DATA3 0H A _CSREN1. . . . . . DATA3 0H A _CSREN2. . . . . . DATA3 0H A _CSREN3. . . . . . DATA3 0H A _CSREN4. . . . . . DATA3 0H A _CSWEN0. . . . . . DATA3 0H A _CSWEN1. . . . . . DATA3 0H A _CSWEN2. . . . . . DATA3 0H A _CSWEN3. . . . . . DATA3 0H A _CSWEN4. . . . . . DATA3 0H A _MCTC0 . . . . . . DATA3 2H A _MCTC1 . . . . . . DATA3 2H A _MCTC2 . . . . . . DATA3 2H A _MCTC3 . . . . . . DATA3 2H A _MCTC4 . . . . . . DATA3 2H A _MTTC0 . . . . . . DATA3 0H A _MTTC1 . . . . . . DATA3 0H A _MTTC2 . . . . . . DATA3 0H A A166 MACRO ASSEMBLER START 08/28/03 20:15:47 PAGE 22 _MTTC3 . . . . . . DATA3 0H A _MTTC4 . . . . . . DATA3 0H A _OWDDIS. . . . . . DATA3 0H A _PWDCFG. . . . . . DATA3 0H A _RDYEN0. . . . . . DATA3 0H A _RDYEN1. . . . . . DATA3 0H A _RDYEN2. . . . . . DATA3 0H A _RDYEN3. . . . . . DATA3 0H A _RDYEN4. . . . . . DATA3 0H A _RDY_AS0 . . . . . DATA3 0H A _RDY_AS1 . . . . . DATA3 0H A _RDY_AS2 . . . . . DATA3 0H A _RDY_AS3 . . . . . DATA3 0H A _RDY_AS4 . . . . . DATA3 0H A _ROMEN . . . . . . DATA3 0H A _ROMS1 . . . . . . DATA3 0H A _RWDC0 . . . . . . DATA3 1H A _RWDC1 . . . . . . DATA3 1H A _RWDC2 . . . . . . DATA3 1H A _RWDC3 . . . . . . DATA3 1H A _RWDC4 . . . . . . DATA3 1H A _SGTDIS. . . . . . DATA3 0H A _STKSZ . . . . . . DATA3 0H A _STKSZ1. . . . . . DATA3 1H A _TOS . . . . . . . DAT16 FC00H A _VISIBLE . . . . . DATA3 0H A _WRCFG . . . . . . DATA3 1H A _XPEN. . . . . . . DATA3 1H A _XPERSHARE . . . . DATA3 0H A main . . . . . . . FAR ---- EXT ASSEMBLY COMPLETE. 0 WARNING(S), 0 ERROR(S)